Fractional-N PLL Delay Control for Phase Error Compensation
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Solution Overview
Problem
Fractional-N PLL frequency generators suffer from low signal/noise ratio due to phase jitter and additional time-variant periodic phase errors, leading to increased implementation costs and energy consumption, especially at higher frequency resolutions and target frequency values.
Innovation Solution
A PLL frequency generator design incorporating a voltage-controlled oscillator, switchable frequency divider, switchable delay unit, and a sigma-delta modulator-based controller to generate control words and divisor values, which compensates for phase errors and improves signal/noise ratio, allowing for efficient and cost-effective implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a non-integer frequency division is used in the feedback branch to achieve frequency spacing smaller than the reference frequency, then the frequency resolution is improved, but additional time-variant periodic phase errors are introduced causing spectral lines and reduced signal/noise ratio
Solution Approach 1:
A delay unit is introduced as an intermediary component between the frequency divider and the phase detector. This delay unit applies a variable delay to the frequency-divided signal, acting as a mediator that compensates for the phase errors generated by non-integer frequency division. The delay unit transforms the problematic phase error into a compensatable delay parameter.
Solution Approach 2:
The system employs a feedback mechanism where the phase detector detects phase differences between the reference signal and the delayed frequency-divided signal, and this phase error information is fed back to control the delay unit. This closed-loop feedback enables continuous compensation of the phase errors caused by fractional-N division.
2Object-generated harmful factors
If traditional phase compensation circuits with delay lines and tuning circuits are used to compensate phase errors, then some phase error compensation is achieved, but the implementation cost and energy consumption increase drastically at higher frequency resolutions and GHz range frequencies
Solution Approach 1:
The invention changes the control parameter from analog voltage tuning (which requires complex tuning circuits and consumes high energy) to digital control words. The delay unit is controlled by digital control words generated by a sigma-delta modulator, allowing precise delay adjustment without the need for energy-intensive analog tuning circuits.
Solution Approach 2:
The patent replaces the mechanical/analog tuning circuit system with a digital control system. Instead of using voltage-controlled delay lines requiring analog tuning circuits, the system uses digitally controlled delay elements, substituting complex analog mechanics with simpler digital logic that consumes less energy.
3Measurement precision
If switchable frequency dividers are used to achieve non-integer frequency division, then frequency resolution is improved, but additional time-variant periodic phase errors are introduced leading to spectral lines
Solution Approach 1:
The delay unit applies a preliminary delay to the frequency-divided signal before it reaches the phase detector. This preliminary action of delaying the signal anticipates and prepares for the phase error compensation, allowing the phase detector to work with pre-adjusted signals that require less correction.
Data Source
AI summary
A PLL frequency generator is disclosed for generating an output signal with a settable target frequency, comprising a) a voltage-controlled oscillator for generating the output signal, b) a switchable frequency divider, which is connected to the voltage-controlled oscillator and is designed to derive from the output signal a frequency-divided signal whose instantaneous frequency depends on a value of an adjustable divisor, c) a switchable delay unit, which is connected to the frequency divider and is designed to generate a delayed signal in that the frequency-divided signal is delayed by delay times that depend on a control word, and d) a controller connected to the switchable delay unit controller and designed to determine the control words. According to the invention, the controller has a sigma-delta modulator and is designed to determine the control words depending on at least one signal provided by the sigma-delta modulator.