PLL Phase Frequency Detector Timing for Linear Charge Pumping
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Solution Overview
Problem
Phase-locked loops (PLLs) face performance degradation due to non-linearity in the charge pump caused by up/down current mismatch in the phase frequency detector, leading to increased phase noise and poor performance, especially due to transistor device mismatch.
Innovation Solution
A new timing/clocking scheme is implemented for the phase frequency detector to generate up and down signals such that up/down current mismatch in the charge pump does not contribute to non-linear distortion, by resetting flip-flops using only the up or down signal, thereby eliminating the impact of current mismatch on the output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional phase frequency detector and charge pump are used, then the PLL can operate, but up/down current mismatch causes non-linear distortion and phase noise
Solution Approach 1:
The patent applies preliminary action by resetting the flip-flops in the phase frequency detector using only the up signal before the down signal can introduce mismatch errors. This timing arrangement ensures that the up/down current mismatch in the charge pump does not contribute to non-linear distortion in the first order, eliminating phase noise before it can degrade PLL performance
2Ease of manufacture
If transistor device mismatch is present in the charge pump, then manufacturing is simplified, but current mismatch causes non-linear operation
Solution Approach 1:
The patent converts the harmful effect of transistor device mismatch into a benefit by using the up signal to reset the flip-flops. This timing scheme causes the up/down current mismatch to appear as a constant DC offset rather than non-linear distortion, allowing the PLL to tolerate larger transistor size variations while maintaining linear operation and reducing phase noise
Data Source
AI summary
Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal. The first and second signals may be up and down signals, respectively, or may be down and up signals, respectively. The phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals with the reset signal. The charge pump receives the first and second signals and generates an output signal indicative of phase error between the reference and clock signals.