Shared Loop Filter PLL Architecture for 3D Die Stacks
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Solution Overview
Problem
Existing phase-locked loops (PLLs) in three-dimensional integrated circuits (3DICs) occupy large die areas, leading to increased total die size and reduced functional capacity per volume unit due to the need for individual loop filters for each die.
Innovation Solution
Implementing a shared loop filter among PLLs in a die stack, where each PLL shares a phase and frequency detector, charge pump, voltage-controlled oscillator, and feedback divider, with a programmable connection element controlling the loop filter's ports to adapt bandwidth and provide selective feedback loops for multiple frequency clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each PLL in a die stack has its own loop filter, then each PLL can operate independently with its own frequency, but the die area increases significantly
Solution Approach 1:
Multiple PLLs in the die stack share a common loop filter resource. The loop filter is time-multiplexed among different PLLs, allowing them to share the same physical hardware component. This merging of resources reduces the total die area while maintaining the ability of each PLL to operate at its required frequency through time-division multiplexing and selective connection.
Solution Approach 2:
The shared loop filter is designed to serve multiple PLLs simultaneously through time-multiplexing. A single loop filter structure performs the filtering function for multiple different PLL circuits at different time intervals, making the component universal and multi-functional. This eliminates the need for separate dedicated loop filters for each PLL, thereby reducing overall die area.
2Area of stationary object
If multiple PLLs share a loop filter, then the die area is reduced, but the complexity of managing shared resources increases
Solution Approach 1:
The shared loop filter is accessed by multiple PLLs through periodic time-multiplexing. Each PLL is connected to the loop filter in alternating time slots, with selection signals periodically switching which PLL gains access to the shared resource. This periodic action manages the complexity by providing a systematic, predictable pattern for resource sharing rather than requiring complex arbitration logic.
Solution Approach 2:
The system dynamically switches connections between PLLs and the shared loop filter based on which PLL needs to lock or adjust its frequency at any given moment. The selection mechanism dynamically activates the appropriate PLL connection to the loop filter, allowing flexible resource allocation that adapts to real-time operational needs while maintaining manageable complexity through controlled dynamic switching.
Data Source
AI summary
An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter.


