PLL Digital Hold Using Averaged Control Word for Clock Holdover
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Solution Overview
Problem
High speed communication systems face challenges in maintaining accurate clock signal generation during holdover mode, where the reference clock signal is lost, due to frequency drift and failure to meet specified accuracy and jitter requirements.
Innovation Solution
A phase-locked loop (PLL) generates an output clock signal using an average digital control word, averaging samples of the digital control value during the presence of the reference signal and applying this average value during its absence, with a low pass filtered and delayed output to reduce quantization noise and improve initial accuracy in holdover mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If feedback is discontinued during holdover mode to maintain output clock signal, then the system can continue operating without reference clock signal, but the output clock signal frequency drifts and fails to meet accuracy requirements
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing an average digital control word during the presence of the reference clock signal before holdover mode begins. This average value is computed from multiple samples of the digital control word, capturing the oscillator's calibrated frequency characteristics. When holdover mode starts, this pre-computed average is immediately applied to the controllable oscillator, eliminating the need for real-time feedback while maintaining frequency accuracy.
2Measurement precision
If multiple samples of digital control word are averaged to improve initial accuracy in holdover mode, then the frequency error specification is met, but the device complexity increases
Solution Approach 1:
The patent implements parameter changes by dynamically adjusting the number of samples averaged and the delay period based on operating conditions. The digital hold circuit is configured to average a first number of samples of the digital control word during reference clock presence and apply them after a second number of samples delay. This configurable approach allows optimization of the balance between initial frequency accuracy and circuit complexity, as different sample counts and delay periods can be selected to meet specific performance requirements without unnecessarily increasing device complexity.
3Adaptability or versatility
If voltage controlled oscillator with high frequency variation over temperature is used, then the PLL can operate across temperature ranges, but the holdover accuracy fails to meet requirements
Solution Approach 1:
The patent applies preliminary action by pre-characterizing the oscillator's frequency behavior across temperature ranges during normal operation with the reference clock present. Multiple samples of the digital control word are collected and averaged, capturing the oscillator's calibrated frequency characteristics including temperature compensation effects. This pre-computed average digital control word is then stored and immediately applied when holdover mode begins, ensuring that the oscillator maintains accurate frequency even with inherent temperature sensitivity, without requiring real-time temperature measurement or adjustment during holdover.
Data Source
AI summary
A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.