PLL Divided Signal Timing Using an Internal Time Reference
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in generating divided signals when the reference clock is unavailable, as they require precise timing and phase offsets, which are difficult to maintain without a stable reference.
Innovation Solution
A clock generation circuit that uses a time reference signal as a substitute for the reference clock, allowing the generation of divided signals with specified offsets, even when the reference clock is unavailable, by employing a multiplexor to select between the reference clock and the time reference signal, and utilizing flip-flops and a delay block to synchronize and offset the signals accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a PLL is used to generate divided signals with precise phase offsets, then the timing precision is improved, but the system becomes unable to operate when the reference clock is unavailable
Solution Approach 1:
An intermediary time reference signal is introduced to bridge the gap between the unavailable reference clock and the PLL. This time reference signal serves as a mediator that allows the PLL to maintain operation and generate divided signals with correct phase offsets even when the original reference clock is unavailable, thus resolving the contradiction between precision and reliability
Solution Approach 2:
The system dynamically changes the reference signal parameter by switching between the normal reference clock and an alternative time reference signal based on availability. When the reference clock becomes unavailable, the system transitions to using the time reference signal, allowing continuous operation while maintaining phase offset precision through parameter adaptation
2Reliability
If the system switches to an alternative time reference when reference clock is unavailable, then the operation continuity is improved, but the phase offset accuracy may deteriorate
Solution Approach 1:
The system performs preliminary actions by pre-establishing the time reference signal and preparing the switching mechanism before the reference clock fails. This allows seamless transition to the alternative reference without losing synchronization information, thereby maintaining both operation continuity and phase offset accuracy simultaneously
Data Source
AI summary
Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.