PLL Frequency Divider Reset Scheme for Fast Phase Locking
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Solution Overview
Problem
Existing phase-locked loops (PLLs) in transceivers face challenges in achieving fast locking due to mutual constraints between stability, dynamic response, accuracy, and noise, making it difficult to improve phase-locking speed without introducing complex circuit structures that can cause noise and alter PLL parameters.
Innovation Solution
A fast-locking phase-locked loop and frequency divider system that includes a phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, fast-locking control unit, and frequency divider, utilizing a reset/set control circuit to transition the frequency divider's state code combination from a first to a second state in response to a reset signal, thereby enabling rapid phase locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the current in the charge pump is changed to accelerate phase locking, then the phase-locking speed is improved, but the circuit structure becomes complex and noise is introduced
Solution Approach 1:
The patent introduces a frequency divider as an intermediary component between the voltage-controlled oscillator and the phase frequency detector. By dividing the feedback frequency before comparison, the system achieves faster phase locking without modifying the charge pump current, thus avoiding the complexity and noise issues associated with changing charge pump parameters
Solution Approach 2:
The patent changes the feedback frequency parameter by introducing a frequency divider with division ratio N. This parameter change allows the phase frequency detector to operate at a lower frequency, improving phase-locking speed while keeping the charge pump structure simple and avoiding noise introduction
2Speed
If the charge pump current is increased to improve dynamic response, then the phase-locking speed is improved, but noise in the PLL system increases
Solution Approach 1:
The frequency divider acts as a mediator that enables fast locking without increasing charge pump current. By reducing the feedback frequency through division, the system achieves faster response while maintaining low noise levels, as the charge pump operates at its original clean signal levels
3Speed
If the charge pump current is changed to accelerate locking, then the phase-locking speed is improved, but PLL parameters are altered making it difficult to widely use
Solution Approach 1:
The frequency divider is a universal component that can be integrated into various PLL architectures without fundamentally changing their operation. The division ratio N can be adjusted to achieve different locking speeds while maintaining compatibility with existing PLL designs, making the solution widely applicable
Solution Approach 2:
The frequency divider serves as a versatile intermediary that can be inserted into different PLL configurations. It provides a universal method for accelerating phase locking that works across various PLL implementations without requiring system-specific modifications to charge pump parameters
Data Source
AI summary
The present disclosure provides a phase-locked loop, a frequency divider and a communication device that enable fast locking. The phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider, wherein the frequency divider comprises a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to receive the reset signal outputted by the fast-locking control unit, and in response to transition of the reset signal from a low level to the high level, change a state code combination composed of respective state codes of the cascaded frequency division units from the first state to the second state, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level. With the frequency divider and phase-locked loop, fast locking can be achieved.