PLL Feedback Divider Preloading for Fast Channel Re-Lock
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Solution Overview
Problem
Phase-Locked Loops (PLLs) in frequency-hopping spread spectrum communication systems require significant settling/locking time to switch between channels, which compromises responsiveness and battery life, as they often need to perform a complete resynchronization procedure upon awakening from sleep mode.
Innovation Solution
A 'clean on-the-fly' PLL re-lock technique where the new channel value is loaded into a PLL feedback divider during a standby phase, allowing quick re-locking with minimal disturbance, reducing channel-hopping time and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complete resynchronization procedure is performed upon awakening from sleep mode, then the PLL achieves frequency stability and accuracy, but the frequency settling and locking time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-loading the new channel value into the feedback divider during the standby phase before the PLL needs to switch channels. This advance preparation allows the PLL to quickly adopt the new frequency without performing a complete resynchronization procedure, thereby reducing the frequency settling time while maintaining frequency stability.
2Speed
If the communication application continuously maintains synchronization, then the responsiveness is improved, but the battery life decreases
Solution Approach 1:
The patent enables the system to enter sleep mode and save battery life by continuously maintaining synchronization in the background. The new channel value is pre-loaded into the feedback divider during standby, so when the communication application needs to wake up and switch channels, it can do so quickly without significant settling time, thus maintaining responsiveness while extending battery life.
3Speed
If the new channel value is loaded into the feedback divider during the counting cycle, then the channel switching is faster, but the edge displacement between reference and feedback waveforms increases causing longer settling time
Solution Approach 1:
The patent introduces a standby phase as an intermediary between the current channel operation and the new channel switching. During this standby phase, the new channel value is loaded into the feedback divider without causing significant edge displacement. This intermediary phase allows the system to prepare for channel switching without disrupting the ongoing counting cycle, thereby achieving fast channel switching without increasing settling time.
4Loss of time
If the new channel value is loaded during the standby phase, then the edge displacement is minimized and settling time is reduced, but the channel hopping time may increase
Solution Approach 1:
The patent applies preliminary action by loading the new channel value into the feedback divider during the standby phase before the actual channel switching occurs. This advance preparation ensures that when the channel switching is initiated, the feedback divider is already configured with the new value, minimizing edge displacement and reducing settling time without significantly increasing the overall channel hopping time.
Data Source
AI summary
A system and method of loading a programmable counter includes storing a first digital divide value in a register. The first digital divide value is then loaded from the register to a programmable counter. The method further includes writing a second digital divide value to the register at a time responsive to a time remaining to complete a counting cycle of the programmable counter.