PLL Divider Gating for Low-Power Clock Lock Maintenance
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Solution Overview
Problem
Phase-locked loops in microprocessors consume large amounts of power due to the need for multiple high-frequency clock generation, making it impractical to supply high-frequency clocks externally and necessitating the use of multiple phased-locked loops, which further increases power consumption.
Innovation Solution
A phased-locked loop circuit design that includes a phase-frequency detector, voltage-controlled oscillator, and divider, where the divider is disabled when the feedback signal is locked to the reference signal, reducing power consumption by minimizing the energy used by the divider and enabling periodic checks for lock status using a frequency lock detector operating at a low duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the divider operates continuously to maintain lock between feedback and reference signals, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The divider is enabled only periodically based on lock status detection. When the PLL is locked, the divider operates intermittently rather than continuously, reducing power consumption while maintaining synchronization accuracy through periodic operation synchronized with the reference clock edge.
2Adaptability or versatility
If multiple phased-locked loops are used to generate high-frequency clocks, then clock generation capability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic operation of the divider based on lock status, allowing the PLL to enter low-power states when locked while maintaining clock generation capability. This periodic activation reduces overall power consumption across multiple PLLs while preserving their ability to generate high-frequency clocks when needed.
3Use of energy by moving object
If the divider is disabled when locked, then power consumption is reduced, but lock detection complexity increases
Solution Approach 1:
The patent uses a frequency lock detector that provides feedback about lock status to control the divider operation. This feedback mechanism automatically adjusts divider activity based on whether the PLL is locked, reducing power consumption without requiring complex manual control logic.
Solution Approach 2:
The PLL system automatically manages its own power consumption by using the lock status to control divider operation. The system self-regulates by enabling the divider only when lock is detected and disabling it when locked, eliminating the need for external power management complexity.
Data Source
AI summary
A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled.