PLL Feedback Divider Reset for Hitless Clock Source Switching
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Solution Overview
Problem
In digital phase-locked loop systems, switching between input clock sources can result in significant phase transients due to large offsets, particularly when switching from a primary input to a secondary input, especially for low-frequency clocks, leading to delays and inaccuracies in phase offset measurement.
Innovation Solution
Implementing a feedback divider reset mechanism using monitoring circuits and a reset circuit to absorb phase offsets between input clock signals, allowing for hitless switching by resetting the feedback clock divider, thereby reducing phase transients and improving measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switching is performed between input clock sources to maintain system operation, then system reliability is improved, but large phase transients occur on the output signal
Solution Approach 1:
The patent measures the phase offset between the current primary input and the secondary input before switching occurs. This preliminary measurement allows the system to prepare compensation values in advance, so that when switching happens, the phase transient is minimized because the offset has already been accounted for in the phase detector's absorption capability.
Solution Approach 2:
The patent changes the operating parameters of the feedback divider by resetting its modulus value during the switching process. By dynamically adjusting the division ratio parameter, the system can absorb the phase offset difference between inputs and maintain a stable output phase, thereby reducing harmful phase transients while ensuring reliable switching.
2Productivity
If phase offset measurement is performed with large offsets, then switching can be implemented, but measurement precision deteriorates and delays occur
Solution Approach 1:
The patent dynamically changes the feedback divider modulus parameter during the measurement process. By adjusting the division ratio, the system can map large phase offsets into a smaller, more measurable range for the phase detector, thereby maintaining measurement precision even when large initial offsets exist between inputs.
Solution Approach 2:
The system performs preliminary phase offset measurement and compensation before the actual switching occurs. This allows the measurement to be done when the offset is still manageable, and the compensation value is prepared in advance, avoiding delays that would occur if measurement had to wait until after switching.
3Stability of the object's composition
If holdover state is maintained for extended periods to ensure stability, then output stability is improved, but phase transients increase due to accumulated offsets
Solution Approach 1:
The patent implements a feedback mechanism where the measured phase offset is continuously monitored and compensated by adjusting the phase detector's absorption. This feedback loop prevents offset accumulation during holdover periods, allowing the system to maintain both stability and minimize phase transients when switching occurs after holdover.
Solution Approach 2:
During holdover operation, the system periodically resets the feedback divider modulus parameter to prevent offset accumulation. By dynamically adjusting this parameter, the system can maintain output stability while ensuring that phase offsets remain within acceptable ranges, thereby reducing phase transients upon subsequent switching.
Data Source
AI summary
An apparatus includes a plurality of monitoring circuits and a reset circuit. The monitoring circuits may each be configured to determine a status of one of a plurality of input signals, transmit one of the input signals to a PLL circuit and generate a loss signal in response to the status. The reset circuit may be configured to receive the loss signal and generate a reset signal in response to the loss signal. One of the input signals may be a primary input used by the PLL circuit. One of the input signals may be a secondary input that has been selected to replace the primary input. The reset signal may be configured to reset a feedback clock divider of the PLL circuit.