PLL Free-Run Divider Trim for Fast Crystal Offset Lock
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Solution Overview
Problem
Phase-locked loops (PLLs) face a significant challenge in quickly nullifying the frequency offset of crystal oscillator clocks during power-on cycles, as the existing DPLL-based methods require considerable time to achieve phase lock, which can be inefficient.
Innovation Solution
The proposed PLL architecture incorporates a free-run control circuit and non-volatile memory to store a frequency control value, allowing the programmable frequency divider to adjust its divide ratio based on both the stored value and dynamically generated frequency control words from the digital loop filter, significantly reducing lock acquisition time by using a pre-configured value during power-on resets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DPLL-based method is used to nullify frequency offset, then phase lock is achieved, but the lock acquisition time is considerable and inefficient
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing frequency control words in non-volatile memory during manufacturing or initial calibration. When the PLL powers on, these pre-computed values are immediately retrieved and applied to the frequency divider, eliminating the need for time-consuming real-time calculation and achieving fast frequency offset compensation from the first power-on cycle
Solution Approach 2:
The patent uses copying by storing copies of frequency control words in non-volatile memory. Instead of recalculating the exact compensation values during operation, the system retrieves stored copies of these control parameters, which are then used to quickly configure the frequency divider and achieve phase lock without lengthy acquisition times
2Reliability
If the frequency divider adjusts divide ratio dynamically, then frequency offset is compensated, but the adjustment process is slow without pre-configured values
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing frequency control words in non-volatile memory during manufacturing or initial calibration. When the PLL powers on, these pre-computed values are immediately retrieved and applied to the frequency divider, eliminating the need for time-consuming real-time calculation and achieving fast frequency offset compensation from the first power-on cycle
Solution Approach 2:
The patent implements feedback by using the TDC to continuously monitor phase differences between reference and feedback clocks, with the digital loop filter processing these measurements and adjusting the frequency divider's divide ratio accordingly. This closed-loop feedback mechanism ensures accurate frequency offset nullification while the pre-stored values provide the initial fast response
Data Source
AI summary
A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.