PLL Divider Control for Wide-Range Overclocking Without Restart
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing over-clocking solutions for processors consume large silicon footprint and power due to the use of LC-oscillator based PLLs, which also provide poor clock jitter performance, and require restarting the PLL for frequency adjustments.
Innovation Solution
A system and method that allows for monotonic over-clocking or under-clocking of a base clock without restarting the PLL, using a phase locked loop (PLL) with a feedback divider and a post locked loop divider, and control logic to adjust divider ratios, extending the frequency range up to 50% with reduced jitter and eliminating the need for additional circuits like phase interpolators or delay locked loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If LC-oscillator based PLL is used for over-clocking, then frequency range can be extended, but silicon footprint and power consumption increase significantly
Solution Approach 1:
The frequency adjustment function is segmented into two independent components: a coarse adjustment mechanism using a feedback divider and a fine adjustment mechanism using a post-PLL divider. This segmentation allows the use of a simple, low-footprint PLL core while achieving wide frequency adjustment range through the combination of two divider stages, thereby resolving the contradiction between frequency range and silicon footprint.
Solution Approach 2:
The invention adds a temporal dimension to frequency adjustment by enabling dynamic reconfiguration of divider ratios during operation. Instead of using a complex high-frequency PLL, the system uses a base-frequency PLL with dynamically adjustable dividers that can be reconfigured in steps, achieving wide frequency range adjustment without increasing the core PLL circuit complexity or footprint.
2Adaptability or versatility
If LC-oscillator based PLL is used for over-clocking, then frequency range can be extended, but power consumption increases due to leakage and active power
Solution Approach 1:
The frequency adjustment function is segmented into two independent components: a coarse adjustment mechanism using a feedback divider and a fine adjustment mechanism using a post-PLL divider. This segmentation allows the use of a simple, low-footprint PLL core while achieving wide frequency adjustment range through the combination of two divider stages, thereby resolving the contradiction between frequency range and silicon footprint.
Solution Approach 2:
The invention replaces the expensive, high-power LC-oscillator based PLL with a simpler, lower-power ring oscillator based PLL. The segmente d divider architecture enables this substitution by providing the necessary frequency adjustment range through software-controlled divider ratios rather than through complex hardware oscillation circuits, significantly reducing power consumption.
3Use of energy by stationary object
If ring oscillator based PLL is used for over-clocking, then power consumption is reduced, but clock jitter performance deteriorates
Solution Approach 1:
The invention introduces dynamic frequency adjustment capability to the ring oscillator based PLL through digitally controllable divider ratios. The feedback divider and post-PLL dividers can be reconfigured in real-time to achieve frequency multiplication and fine-tuning, enabling the simple ring oscillator to produce stable, low-jitter clock signals across a wide frequency range while maintaining low power consumption.
Solution Approach 2:
The invention implements a feedback mechanism where the PLL lock status is monitored and used to control frequency adjustments. The system only adjusts divider ratios when the PLL is properly locked, ensuring stable clock output and minimizing jitter. This feedback control enables reliable frequency adjustment while maintaining the low-power advantage of ring oscillators.
4Speed
If traditional PLL is used for frequency adjustment, then frequency can be changed, but PLL must be restarted which causes time loss
Solution Approach 1:
The invention introduces dynamic frequency adjustment capability to the ring oscillator based PLL through digitally controllable divider ratios. The feedback divider and post-PLL dividers can be reconfigured in real-time to achieve frequency multiplication and fine-tuning, enabling the simple ring oscillator to produce stable, low-jitter clock signals across a wide frequency range while maintaining low power consumption.
Solution Approach 2:
The invention prepares multiple pre-configured divider ratio combinations in advance, allowing the system to switch between frequency settings by simply changing divider values rather than restarting the PLL. This preliminary preparation of adjustment parameters enables instantaneous frequency changes without PLL restart, eliminating time loss while maintaining frequency stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and low-jitter frequency adjustments of the base clock without restarting the PLL, reducing power consumption and silicon footprint, and providing a wider over-clocking range while maintaining lock, thus enhancing processor performance.
Implementation Method 1
A locked loop (e.g., phase locked loop (PLL) or frequency locked loop (FLL)) having a feedback divider. In one embodiment, the locked loop receives a reference clock (Ref Clock) and compares it with a feedback clock (FB Clock) which is output from the feedback divider, and generates an output clock.
Data Source
AI summary
Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.