PLL Divider Pause Control for Faster Lock After Calibration
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Solution Overview
Problem
Phase-locked loop circuits face increased lock time and power consumption due to lingering transitions from frequency calibration, leading to latency in generating a stable clock signal.
Innovation Solution
A phase-locked loop circuit with a programmable divider chain that generates a pause signal to hold divider stages in a particular logic state during frequency calibration, minimizing phase difference and enabling phase resetting to reduce lock time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequency calibration operation is performed on the phase-locked loop circuit, then the oscillator circuit frequency is adjusted to match target frequency, but the divider stages produce lingering transitions that increase lock time and power consumption
Solution Approach 1:
The pause signal is generated in advance at the conclusion of frequency calibration to preemptively halt divider stage transitions. This preliminary action prevents lingering transitions from occurring, thereby reducing lock time without affecting the frequency accuracy achieved during calibration.
Solution Approach 2:
The harmful lingering transitions from the divider stages are extracted and eliminated by introducing the pause signal. This separates the frequency calibration function from the phase locking function, allowing the divider to be reset independently and preventing it from extending the lock time.
2Measurement precision
If frequency calibration operation is performed on the phase-locked loop circuit, then the oscillator circuit frequency is adjusted to match target frequency, but the lingering transitions from divider stages increase power consumption
Solution Approach 1:
The pause signal is generated in advance at the conclusion of frequency calibration to preemptively halt divider stage transitions. This preliminary action prevents harmful transitions from occurring, thereby reducing power consumption without affecting the frequency accuracy achieved during calibration.
Solution Approach 2:
The harmful lingering transitions from the divider stages are extracted and eliminated by introducing the pause signal. This separates the frequency calibration function from the phase locking function, allowing the divider to be reset independently and preventing it from consuming excess power during the locking phase.
3Adaptability or versatility
If the divider stages continue operating during frequency calibration, then the frequency adjustment can be performed, but phase difference between divider output and reference signal increases causing latency
Solution Approach 1:
The pause signal is generated in advance at the conclusion of frequency calibration to preemptively halt divider stage transitions. This preliminary action ensures that when phase locking begins, the divider is already in a stable state, eliminating latency in generating a valid clock signal while preserving frequency adjustment capability.
Solution Approach 2:
The pause signal acts as an intermediary between the frequency calibration operation and the phase locking operation. It mediates the transition by resetting the divider stages to a known state, ensuring smooth handoff and minimizing latency in generating a valid clock signal.
Data Source
AI summary
In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.