PLL Feedback Divider Matching Reference Clock Period Error
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Solution Overview
Problem
Frequency synthesizers in communication systems face performance degradation due to low-frequency additive noise from oscillators, which is converted to phase noise, affecting the reference clock signal and ultimately the data communication link.
Innovation Solution
A method and apparatus that utilize a phase-locked loop with a phase and frequency detector, a feedback divider, and a delta sigma modulator to generate a feedback clock signal with a period error matching the reference clock signal, using different divide values for odd and even cycles based on an error term determined by a covariance matrix to correct period errors in the reference clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a sine-to-rectangular wave converter is used to generate reference clock signal, then the frequency synthesizer becomes less susceptible to noise sources, but low frequency additive noise is converted to phase noise affecting performance
Solution Approach 1:
The patent converts the harmful period error in the reference clock signal into a beneficial correction mechanism. By detecting the period error and intentionally introducing a matching error into the feedback clock signal, the system cancels out the harmful effects at the phase detector input, transforming the original noise problem into a solution that improves phase noise performance
Solution Approach 2:
The patent implements a feedback mechanism where the period error detected from the reference clock signal is fed back through the feedback divider to generate a corrected feedback clock signal. This feedback loop continuously compensates for the period error, reducing phase noise and improving overall system performance
2Object-generated harmful factors
If conventional phase noise correction methods are used, then phase noise may be reduced, but slow edges or shallow slopes are required which degrade signal quality
Solution Approach 1:
The patent converts the harmful period error into a beneficial correction by intentionally introducing a matching error in the feedback path. This approach reduces phase noise without requiring slow edges or shallow slopes, maintaining sharp signal edges and high signal quality while achieving noise reduction
Solution Approach 2:
The patent changes the divide values of the feedback divider based on detected period error parameters. By dynamically adjusting the divide values to compensate for period errors, the system reduces phase noise while maintaining optimal signal edge characteristics
Data Source
AI summary
A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.