PLL Feedback Divider Switching for Faster Phase Lock
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in reducing the initial phase error, which prolongs the locking time, especially for type-I PLLs where the target locking phase is non-zero (ΔΦ LCK >0).
Innovation Solution
The solution involves configuring the feedback divider in the PLL to set its division value during the first division cycle such that the phase relationship between the reference and feedback signals matches the target locking phase (ΔΦ LCK ), thereby achieving zero initial phase error, which is synchronized with the reference signal and optionally delayed to minimize transient effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the feedback divider uses a fixed division value from the start, then the PLL operation is simple, but the initial phase error is non-zero which prolongs the locking time
Solution Approach 1:
The feedback divider is configured to use a first division value during an initial period before the PLL achieves lock, rather than using the nominal division value from the start. This preliminary action with a different division value enables the feedback signal to reach the correct phase relationship with the reference signal earlier, reducing the initial phase error and thereby reducing the locking time without requiring complex real-time adjustments during normal operation
Solution Approach 2:
The feedback divider transitions from a static fixed division value to a dynamic configuration where it uses different division values at different times: a first division value during the initial period and a nominal division value during normal operation. This dynamic approach allows the system to optimize for fast locking initially, then maintain stable operation, resolving the contradiction between simple operation and fast locking
2Loss of time
If the division value is changed dynamically to reduce initial phase error, then the locking time is reduced, but the control complexity increases
Solution Approach 1:
The system performs a preliminary configuration of the feedback divider with a first division value before the PLL locking process begins. This preliminary setup simplifies the overall operation because the divider automatically uses the optimized division value during the critical initial phase without requiring complex real-time control logic or manual intervention during the locking process itself
Solution Approach 2:
The feedback divider operates in two distinct periodic phases: an initial period where it uses the first division value to minimize phase error, and a subsequent normal operation period where it uses the nominal division value. This periodic switching approach maintains operational simplicity while achieving fast locking, as the transition follows a predetermined timing pattern rather than requiring complex continuous adjustment
Data Source
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AI summary
Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.