PLL Divider Reset Initialization for Faster Lock Acquisition
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Solution Overview
Problem
Phase lock loops (PLLs) with high-Q oscillators require long lock times due to narrow loop bandwidths, limited VCO tuning ranges, and the need to slew the VCO tune voltage over a large frequency and phase range, which is exacerbated by high divider ratios and low reference frequencies.
Innovation Solution
Incorporating a reset circuit that presets the phase difference between the PLL feedback signal and the reference signal to the lock angle, using a delay circuit or programmable counter to align the phase, and optionally employing a frequency multiplier to increase frequency resolution, allowing the PLL to initialize more quickly by reducing the necessary phase correction distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a narrow loop bandwidth is used to preserve VCO phase noise in high-Q resonator PLLs, then phase noise performance is improved, but lock time is significantly extended
Solution Approach 1:
The patent applies preliminary action by presetting the frequency divider to a predetermined initial value before starting the locking process. This initial value is calculated based on the expected lock angle and system parameters, allowing the PLL to start from a phase position closer to the locked state, thereby reducing lock time without requiring a wider loop bandwidth that would degrade phase noise performance.
2Adaptability or versatility
If a high divider ratio N is used to achieve the required output frequency, then frequency range is improved, but lock time is extended due to limited VCO tuning range
Solution Approach 1:
The patent calculates and sets an initial frequency divider value based on the relationship N_initial = N_final + (lock_angle × F_REF)/(2π × F_VCO) before the locking process begins. This preliminary calculation positions the VCO frequency closer to the target frequency, reducing the phase rotation time required during locking, thus enabling high divider ratios without proportionally increasing lock time.
3Adaptability or versatility
If a low reference frequency is used to achieve high output frequency with high divider ratio, then frequency multiplication capability is improved, but lock time is extended due to slower phase rotation
Solution Approach 1:
The patent compensates for the slow phase rotation at low reference frequencies by calculating an optimized initial frequency divider value that accounts for the relationship between reference frequency, lock angle, and VCO frequency. This preliminary setting reduces the number of phase rotations needed during locking, enabling the system to achieve high frequency multiplication capability without proportionally increasing lock time.
Data Source
AI summary
A phase lock loop (PLL) includes a phase detector configured to output a signal indicative of a phase difference between a reference signal and a feedback signal, a loop filter configured to filter an output of the phase detector, and a voltage-controlled oscillator (VCO) configured to output an oscillating signal having a frequency corresponding to an output of the loop filter. The PLL further includes a frequency divider configured to output the feedback signal by frequency dividing the oscillating signal output by the VCO, and a reset circuit configured to reset the frequency divider in an initialization mode such that a phase difference between the reference signal and the feedback signal corresponds to a lock angle of the PLL.