PLL Synchronization Using Divider Restart for Faster Phase Lock
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Solution Overview
Problem
Phase-locked loop (PLL) devices face challenges in reducing lock time, especially when operating with low open loop gain, and in synchronizing multiple PLL devices to achieve desired time-shifts between frequency-converted and reference signals.
Innovation Solution
Incorporating synchronization units that temporarily suspend and restart the frequency divider operation based on signal transitions, ensuring the frequency-converted signal is synchronized with the reference signal at restart, and using a common reference signal and frequency division ratio for multiple PLL devices to achieve simultaneous synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the PLL device operates with low open loop gain to reduce noise, then noise levels are maintained low, but lock time increases significantly
Solution Approach 1:
The synchronization unit performs preliminary actions by detecting signal transitions in advance and proactively stopping the frequency divider before the phase error becomes significant. This preemptive approach allows the system to maintain low gain operation while avoiding long lock times, as the divider is stopped and restarted at optimally timed moments based on detected transitions in the reference or frequency-converted signals.
2Adaptability or versatility
If multiple PLL devices operate independently with different phase trajectories, then each device can be optimized independently, but synchronization between devices becomes difficult to achieve
Solution Approach 1:
The synchronization unit acts as an intermediary mechanism that mediates between multiple independently operating PLL devices. By monitoring signal transitions and controlling the frequency divider's stop/start timing, it synchronizes the phase trajectories of multiple devices without requiring them to be identical or pre-coordinated, thus maintaining independent operation while achieving reliable synchronization.
3Productivity
If the frequency divider operates continuously to maintain frequency conversion, then frequency conversion is maintained, but phase synchronization with reference signal becomes difficult to achieve
Solution Approach 1:
The frequency divider operates periodically rather than continuously - it is stopped and restarted at specific intervals determined by signal transitions. This periodic operation allows the system to maintain frequency conversion capability while achieving precise phase alignment, as the divider is active during conversion periods and synchronized during stop periods based on detected transitions in the reference or frequency-converted signals.
Data Source
AI summary
A phase-locked loop (PLL) device includes synchronization means suitable for synchronizing a frequency-converted signal produced by a frequency divider of the PLL device, with a reference signal supplied to the PLL device. A time duration of a frequency/phase lock acquisition step which is performed upon starting an operation of the PLL device can be reduced. In addition, when operating several PLL devices simultaneously, the synchronization units allow recovering target values for phase differences that exist between the respective frequency-converted signals of the PLL devices. To this end, synchronization is requested at a same time for all the PLL devices after they are all running in locked state.