Programmable Frequency Divider With Single-Counter PLL Architecture
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Solution Overview
Problem
Existing programmable frequency dividers in frequency synthesizers have high power consumption due to high fan-out and unnecessary parallel operation of counters, which increases manufacturing costs and reduces operation performance at high frequencies.
Innovation Solution
A programmable frequency divider that replaces two counters with a single counter module, performing sequential swallow mode and program mode counting, and uses a control signal generator to adjust the divide ratio and generate reset signals, reducing fan-out and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If two counters (swallow counter and program counter) operate in parallel to divide high-speed clocks, then the frequency division function is achieved, but power consumption significantly increases
Solution Approach 1:
The patent merges the swallow counter and program counter into a single counter module that can operate in different modes. The single counter replaces two separate counters, reducing power consumption while maintaining the frequency division functionality through mode switching controlled by the divide ratio control signal.
Solution Approach 2:
The single counter is designed to perform multiple functions by switching between swallow mode and program mode. This multi-functional counter can count up to different values (S for swallow mode, P for program mode) and control the divide ratio accordingly, eliminating the need for separate dedicated counters.
2Speed
If the divided clock is supplied simultaneously to two counters, then both counters can perform counting functions, but fan-out becomes very high reducing operation performance at high frequencies
Solution Approach 1:
The patent combines the clock input paths for both counters into a single clock input for the unified counter module. This reduces the fan-out of the divided clock signal from two separate counter inputs to a single counter input, improving high-frequency operation performance.
Solution Approach 2:
The counter dynamically switches between swallow mode and program mode based on the divide ratio control signal. This dynamic mode switching allows the single counter to adapt its counting behavior, replacing the static parallel operation of two separate counters and reducing clock distribution complexity.
3Ease of manufacture
If two counters perform the same counting function in parallel, then frequency division is achieved, but chip area increases resulting in increased manufacturing costs
Solution Approach 1:
The patent merges two separate counter circuits into a single counter module, directly reducing the chip area occupied by counter logic. This consolidation eliminates redundant circuitry while maintaining the frequency division function through mode-controlled operation.
Solution Approach 2:
The single counter is designed with multi-functionality to perform both swallow counting and program counting tasks that previously required two separate counters. This universal counter reduces chip area by eliminating the need for duplicate counter structures.
Data Source
AI summary
A programmable frequency divider, which is a core module of a frequency synthesizer using a Phase Locked Loop (PLL) for generating very high frequencies, includes a divided clock generator dividing a frequency of an input clock signal Fin by a first divide ratio (N+1) or a second divide ratio N according to a divide ratio control signal MC to generate a plurality of divided clock signals Dout; a counting unit counting the number CNT of the plurality of divided clock signals Dout, by performing swallow mode counting and program mode counting sequentially on the plurality of divided clock signal Dout; a control signal generator generating the divide ratio control signal MC, using the number CNT of the plurality of divided clock signal Dout, a count S by the swallow mode counting and a count P by the program mode counting, the count P corresponding to a maximum of the number CNT, feeding the divide ratio control signal MC back to the divided clock generator, and generating a reset control signal RST for resetting the counting unit.