PLL Phase Comparator Without Frequency Divider for Low Current
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Solution Overview
Problem
The phase locking circuit in semiconductor devices consumes a significant amount of electric current due to the frequency division circuit, which also requires a large area, making it inefficient for energy harvesting applications at several tens of MHz frequencies.
Innovation Solution
The phase locking circuit is modified by replacing the frequency division circuit with a delay flip flop as the phase comparator, allowing direct phase detection of the voltage-controlled oscillator's output, thereby reducing electric current consumption without increasing the circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency division circuit is used in the phase locking circuit, then the phase and frequency can be compared between reference input signal and feedback signal, but the consumed electric current becomes large (about thirty percent of the entire consumed electric current)
Solution Approach 1:
The patent extracts and removes the frequency division circuit from the traditional PLL structure. By using a delay flip-flop to directly sample the VCO output phase, the system eliminates the need for frequency division, thereby removing the source of high current consumption while preserving the essential phase comparison function through direct sampling of the oscillation signal.
Solution Approach 2:
The patent replaces the mechanical frequency division operation with an electronic sampling mechanism using a delay flip-flop. Instead of dividing the frequency through sequential counting operations, the system uses synchronized sampling at specific phase points to directly obtain phase information, substituting a high-current mechanical division process with a low-current electronic sampling process.
2Speed
If an LC oscillator is used to achieve several tens of MHz operation, then the oscillation frequency can be achieved, but the area becomes 4000 times as large as a Ring oscillator
Solution Approach 1:
The patent changes the fundamental operating parameters of the oscillator by transitioning from an LC oscillator architecture to a Ring oscillator architecture. This parameter change involves adjusting the oscillation mechanism from resonant LC tank circuits to cascaded inverter stages with feedback, enabling several tens of MHz operation with dramatically reduced area while maintaining the required frequency performance through optimized stage count and loading conditions.
3Use of energy by moving object
If a Sub-Sampling PLL is used to remove the frequency division circuit, then the consumed electric current can be reduced, but the circuit area becomes large due to LC oscillator requirements
Solution Approach 1:
The patent merges the oscillator function with the phase detection function by using the Ring oscillator output directly as the signal to be sampled by the delay flip-flop. This integration eliminates the need for separate frequency division circuitry and large-area LC resonators, combining multiple functions into a compact unified structure that achieves both low current consumption and small area.
Data Source
AI summary
A phase locking circuit includes: a phase comparator; a pulse generation circuit; a charge pump circuit; a loop filter circuit; and a voltage-controlled oscillator. The phase comparator samples a first level in synchronization with a received reference clock, and generates a first signal to be initialized to a second level that is different from the first level by using a feedback clock. The pulse generation circuit generates a second signal in accordance with the reference clock, and controls a phase of as output signal of the voltage-controlled oscillator to be the feedback clock to have a predetermined value by inputting the first signal and the second signal as a control voltage to the voltage-controlled oscillator through the charge pump circuit and the loop filter circuit.