PLL and DLL Restart Using Stored Loop Filter Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase-locked loops (PLLs) and delay-locked loops (DLLs) face challenges in rapidly restarting from a sleep state to an active state, leading to prolonged locking times and increased power consumption due to the need for frequent synchronization and phase alignment.
Innovation Solution
The implementation of a PLL and DLL that alternate between sleep and active states, utilizing a synchronizer and loop filter to maintain frequency and phase information during the sleep state, allowing for rapid restart by synchronizing the frequency-divided output signal with the reference signal upon activation, thus reducing locking time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the PLL or DLL is continuously kept in the active state to maintain frequency and phase synchronization, then rapid restart is achieved, but unnecessary power is consumed
Solution Approach 1:
The loop filter maintains frequency and phase information from the previous active state during the sleep state, preparing the system for rapid restart without requiring full re-synchronization. This preliminary preservation of critical parameters enables quick recovery when transitioning back to active state.
Solution Approach 2:
The system dynamically adapts its operation mode by switching between active and sleep states based on whether rapid restart is needed. The loop filter's behavior changes from active filtering during operation to information preservation during sleep, optimizing both power consumption and restart performance.
2Use of energy by moving object
If the PLL or DLL is restarted from sleep state to active state, then power consumption is reduced, but locking time increases
Solution Approach 1:
Critical synchronization information including frequency and phase data is preserved in the loop filter before entering sleep state. This preliminary action eliminates the need for time-consuming re-synchronization procedures when restarting, reducing locking time while maintaining power savings.
Solution Approach 2:
The loop filter creates and maintains a copy of the frequency and phase information from the synchronized state. This copied information serves as a template for rapid re-synchronization upon restart, avoiding the need to regenerate these parameters from scratch.
3Reliability
If numerous iterations are performed to achieve frequency and phase synchronization, then accurate locking is achieved, but locking time increases
Solution Approach 1:
The system performs preliminary synchronization to establish accurate frequency and phase relationships before entering sleep mode. The loop filter captures and preserves this pre-established synchronization information, eliminating the need for numerous iterative adjustments during restart while maintaining synchronization accuracy.
Data Source
AI summary
Disclosed is a phase-locked loop and a delay-locked loop. When the phase-locked loop switches from a sleep state to an active state, a frequency of a reference signal is the same as a frequency of a reference signal which has been synchronized in a previous active state. The phase-locked loop alternately operates in a sleep state and an active state. A frequency-divided output signal of the phase-locked loop is synchronized with a frequency-divided reference signal, when the phase-locked loop switches from a sleep state to an active state, a frequency of the frequency-divided output signal is identical to a frequency of a frequency-divided output signal which has been synchronized in a previous active state. Information corresponding to the frequency of the frequency-divided output signal which has been synchronized in the previous active state is stored in a capacitor.