PLL-DLL Time-to-Digital Converter for Stable ToF Resolution
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Solution Overview
Problem
Conventional time-to-digital converters in LIDAR systems have limitations such as single-channel operation, high dependence on inverter delay, narrow detectable time range, and instability due to external environmental changes, making it difficult to achieve stable high resolution.
Innovation Solution
A time-to-digital converter utilizing a phase locked loop (PLL) and delay locked loop (DLL) to precisely measure time differences between start and stop signals, decomposing reference clocks into multi-phase clocks, and recording edge positions for both rising and falling edges, allowing for high-resolution distance measurement and noise correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional Vernier inverter structure is used, then the device is simple to manufacture, but the resolution is unstable due to high dependence on inverter delay and external environmental changes
Solution Approach 1:
The patent divides the time measurement process into multiple independent channels (first channel with first Vernier inverter chain, second channel with second Vernier inverter chain). Each channel operates independently to measure different aspects of the time interval, and their results are combined to achieve both high resolution and environmental stability through differential measurement
Solution Approach 2:
The patent changes the operating parameters by using multiple channels with different inverter chain configurations and combining their measurements. This allows the system to maintain high resolution while compensating for environmental variations through parameter diversity across channels
2Device complexity
If a single-channel conventional TDC is used, then the device complexity is low, but the detectable time range is narrow
Solution Approach 1:
The patent segments the time measurement function across multiple channels, where each channel handles a portion of the measurement task. This segmentation enables the system to cover a wider time range by combining results from multiple channels while keeping individual channel complexity manageable
3Loss of time
If multiple channels are added to expand detectable time range, then the time measurement capability is improved, but the device complexity increases
Solution Approach 1:
The patent designs multiple channels that share common functional blocks and control logic, making each channel multi-functional. The channels can operate independently or in combination, allowing the system to achieve extended time range measurement capability while reusing hardware resources to minimize complexity increase
Data Source
AI summary
A time-to-digital converter and a converting method are provided. The time-to-digital converter includes: a phase locked loop unit configured to multiply an input reference clock by using a phase locked loop (PLL); a counting unit configured to count the multiplied input reference clock and record an edge position of an input signal; a delay locked loop unit configured to decompose the multiplied input reference clock into a multi-phase clock using a delay locked loop (DLL), and sense the recorded edge position of the input signal among the decomposed multi-phase clock and record a fine edge position; and a control unit configured to calculate a time difference in time of flight (ToF) between a start signal and a stop signal of the input signal by using the recorded edge position and the recorded fine edge position.