PLL Oscillator Drive Switching for Fast Lock and Low Jitter
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Solution Overview
Problem
Conventional PLL circuits face challenges in generating a clock signal with improved jitter characteristics due to noise in the reference signal, which affects the lockup time and stability of the clock signal frequency matching the target frequency, especially when the drive capability of the inverting amplifier circuit is switched between startup and normal states.
Innovation Solution
A phase locked loop circuit with a crystal oscillator part that controls the drive capability of the inverting amplifier circuit based on a control signal, adjusting it stepwise to optimize the jitter characteristics by increasing the drive capability at startup for quick lockup and reducing noise in the normal state, thereby stabilizing the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the drive capability of the inverting amplifier circuit is increased at startup, then the lockup time is shortened, but the noise in the reference signal increases and jitter characteristics deteriorate
Solution Approach 1:
The patent applies dynamics by making the drive capability of the inverting amplifier circuit variable rather than fixed. The drive capability is dynamically adjusted based on the operational state of the PLL circuit - using high drive capability during startup to shorten lockup time, and switching to low drive capability during normal operation to reduce noise and improve jitter characteristics. This is achieved through a drive capability control circuit that receives a control signal from the PLL circuit to automatically switch between high and low drive capabilities.
2Object-affected harmful factors
If the drive capability of the inverting amplifier circuit is reduced in normal state, then the jitter characteristic is improved, but the lockup time at startup increases
Solution Approach 1:
The patent resolves this contradiction by implementing dynamic control of the inverting amplifier circuit's drive capability. During normal operation, the drive capability is set to low to minimize noise and improve jitter characteristics. During startup, the drive capability is automatically switched to high to ensure quick lockup. The drive capability control circuit monitors the PLL circuit's operational state and automatically adjusts the drive capability accordingly, eliminating the need to choose between these conflicting requirements.
3Reliability
If the drive capability is switched between startup and normal states, then both lockup time and jitter characteristic are optimized, but the circuit complexity increases
Solution Approach 1:
The patent applies universality by designing the drive capability control circuit to perform multiple functions: it monitors the operational state of the PLL circuit, determines whether startup or normal operation is occurring, and controls the switching of the inverting amplifier circuit's drive capability. This multi-functional approach allows the system to optimize both lockup time and jitter characteristics without requiring separate control circuits for each function, thereby minimizing the increase in circuit complexity while achieving overall performance optimization.
Data Source
AI summary
A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal.