PLL DTC Path Swapping for Error and Dither Noise Cancellation
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Solution Overview
Problem
Digital-to-time convertor (DTC) errors lead to mismatch and low-frequency noise in Phase-Locked Loop (PLL) circuits, particularly in all-digital phase-locked loops (ADPLL), due to variance in pressure, temperature, or voltage, which existing technologies fail to effectively address without digital calibration.
Innovation Solution
A PLL circuit with a first and second selection circuit, and DTCs that alternately swap the paths for the reference and feedback signals, applying the same delay control signal for two consecutive cycles to ensure the same error/noise is applied to both paths, allowing DTC errors to cancel out in subsequent stages without the need for digital calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DTC is used to delay reference signal edges, then signal timing control is achieved, but DTC error terms are generated due to pressure, temperature, or voltage variance
Solution Approach 1:
The patent applies the copying principle by duplicating the DTC error terms through symmetric signal paths. The reference signal and feedback signal are routed through matched DTC paths, causing identical error terms to be generated in both paths. These copied error terms then cancel each other out in the phase detector, effectively eliminating DTC errors without requiring additional calibration circuits.
Solution Approach 2:
The patent converts the harmful DTC error terms into a beneficial cancellation mechanism. By intentionally routing both reference and feedback signals through DTCs with identical delay control, the harmful error terms are transformed into matching error patterns that subtract from each other, turning the original problem into a solution that actively cancels the errors.
2Reliability
If DTC error terms are generated, then mismatch and low-frequency noise occur in PLL circuit, but digital calibration is required to correct
Solution Approach 1:
The patent eliminates the need for digital calibration by using symmetric DTC paths that copy error terms into both signal paths. This structural symmetry causes errors to naturally cancel without requiring external calibration circuits or algorithms, thereby reducing device complexity while maintaining high reliability.
Solution Approach 2:
The patent implements self-service by designing the PLL circuit to automatically cancel its own DTC errors through the symmetric path configuration. The circuit structure itself provides the error cancellation mechanism without requiring external calibration systems, making the system self-correcting and reducing overall complexity.
3Productivity
If reference signal and feedback signal are routed through separate DTC paths, then signal processing is achieved, but DTC mismatch errors persist
Solution Approach 1:
The patent applies local quality by ensuring that corresponding signal paths (reference and feedback) have identical local characteristics through matched DTC configurations. Each path is designed with the same delay control properties, creating local symmetry that ensures error terms are identical in both paths, thereby enabling precise error cancellation while maintaining efficient signal processing.
Data Source
AI summary
A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.