PLL Clock Generator DTC Gain Calibration for Faster Locking
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Solution Overview
Problem
Existing digital-to-time converter (DTC) circuits in phase locked loop (PLL) systems face challenges in quickly deriving the gain value required for effective operation, leading to prolonged locking times for clock signal generators.
Innovation Solution
A clock signal generator and phase locked loop circuit design that includes a digital-to-time converter (DTC) and a DTC controller, which determines an initial gain value by comparing delay amounts with the period of a previously generated output clock signal, using a binary search algorithm to quickly derive the gain value and calibrate the delay amount, thereby reducing locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional DTC circuit is used in a PLL system, then the circuit can generate delayed clock signals, but the time required to derive the gain value is prolonged, leading to increased locking time
Solution Approach 1:
The patent applies preliminary action by pre-calibrating the DTC gain value through a systematic procedure. The DTC controller performs a binary search algorithm to determine the optimal gain value before the PLL locking process begins. This pre-calibration ensures that when the PLL operation starts, the gain value is already optimized, thereby reducing the overall locking time without compromising the delay accuracy of the DTC circuit.
Solution Approach 2:
The patent implements feedback by using the DTC controller to continuously monitor the PLL locking status and adjust the DTC gain value accordingly. The controller compares the phase difference between the reference clock signal and the feedback clock signal, and based on this feedback, dynamically optimizes the gain value. This closed-loop feedback mechanism ensures rapid convergence to the correct gain value, significantly reducing the locking time while maintaining signal integrity.
2Loss of time
If the DTC gain value is derived quickly using a binary search algorithm, then the locking time is reduced, but the device complexity increases due to the need for additional control logic
Solution Approach 1:
The patent applies universality by designing the DTC controller to perform multiple functions within a single integrated circuit block. The controller not only derives the gain value using a binary search algorithm but also manages the overall DTC operation, monitors PLL locking status, and adjusts delay amounts dynamically. By consolidating these diverse functions into one multi-functional controller, the patent reduces the need for separate dedicated circuits for each function, thereby minimizing the increase in device complexity while achieving rapid gain value derivation.
Solution Approach 2:
The patent merges the gain value derivation logic, delay control logic, and PLL status monitoring logic into a single integrated DTC controller unit. This consolidation combines multiple control functions that would traditionally require separate circuits into one unified structure. The binary search algorithm for gain derivation is integrated directly into the controller's decision-making logic, eliminating the need for external control circuits and reducing overall system complexity despite the enhanced functionality.
Data Source
AI summary
Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.