Dual-Detector PLL Frequency Acquisition Without Divider Circuits
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Solution Overview
Problem
High-frequency phase locked loops (PLLs) face challenges in achieving a locked state due to tolerance limitations of phase detectors and require complex circuits, including dividers and frequency counters, which increase time and complexity to achieve frequency synchronization.
Innovation Solution
A PLL design incorporating two phase detectors and an adjustor to determine which phase detect signal commutes first, allowing for frequency adjustments of the feedback signal without a divider in the acquisition path or frequency counter, enabling faster locking and reduced circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase detectors are used in high-frequency PLLs, then frequency synchronization can be achieved, but the tolerance limitations of phase detectors require complex circuits including dividers and frequency counters which increase time and complexity to achieve locking
Solution Approach 1:
The invention divides the phase detection function into two separate phase detectors: a first phase detector for coarse frequency acquisition and a second phase detector for fine frequency adjustment. This segmentation allows each detector to operate within optimal tolerance ranges, eliminating the need for complex dividers and frequency counters while achieving accurate frequency synchronization at high frequencies
Solution Approach 2:
The first phase detector performs preliminary frequency acquisition by detecting phase differences over a wider range, bringing the feedback frequency close to the reference frequency before the second phase detector takes over for fine-tuning. This preliminary action reduces the initial frequency offset, enabling faster locking without complex acquisition circuits
2Measurement precision
If dividers and frequency counters are added to improve frequency measurement accuracy, then locking accuracy improves, but the time to achieve locked state increases
Solution Approach 1:
The system dynamically switches between two phase detection modes: the first phase detector operates during acquisition to provide fast coarse frequency adjustment, then the second phase detector takes over for precise fine-tuning during locking. This dynamic transition eliminates the need for time-consuming frequency counting while maintaining measurement accuracy throughout the locking process
3Reliability
If complex acquisition circuits are used to overcome phase detector tolerance limitations, then frequency synchronization accuracy improves, but the overall system complexity increases
Solution Approach 1:
The acquisition function is segmented between two phase detectors with different detection ranges and characteristics. The first detector handles large frequency offsets with simplified logic, while the second detector handles small offsets with higher precision, achieving reliable synchronization without complex acquisition circuits
Solution Approach 2:
The first phase detector acts as an intermediary that prepares the frequency relationship between reference and feedback signals by reducing the frequency offset, enabling the second phase detector to achieve accurate locking with simpler and more reliable detection logic
Data Source
AI summary
A phase locked loop that includes a signal generator arranged to output a feedback signal, a first phase detector arranged to detect a phase difference between the feedback signal and a reference signal and to output a first phase detect signal in dependence on that detection, a second phase detector arranged to detect a phase difference between the feedback signal and a delayed version of the reference signal or between the reference signal and a delayed version of the feedback signal and to output a second phase detect signal in dependence on that detection, and an adjustor. The adjustor is arranged to determine which of the first and second phase detect signals commutes first and to alter the frequency of the feedback signal in dependence on the result of the determination.