PLL Dual-Edge Lock Detection for False Lock Prevention
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Solution Overview
Problem
Conventional phase locked loop (PLL) circuits face challenges in accurately and efficiently detecting when the PLL output has locked onto a reference signal, often resulting in false positive lock indications due to the instability of frequency stabilization during power-up and potential misalignment between reference and feedback signals.
Innovation Solution
A lock detector circuit utilizing dual edge-triggered flip flops and a timing circuit with a counter or firmware to assess the phase alignment between a reference signal and a feedback signal, ensuring accurate lock detection by considering both rising and falling edges and resetting the timing operation when out of phase conditions are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional lock detector compares reference and feedback signals to detect lock condition, then the PLL system can generate clock gating signals, but false positive lock indications occur due to frequency instability during power-up
Solution Approach 1:
The patent applies preliminary action by implementing a delay mechanism before asserting the lock signal. The lock detector circuit waits for a predetermined time period after detecting phase alignment between reference and feedback signals before generating the final lock indication. This preliminary waiting period allows frequency stabilization and prevents false positive lock indications during the unstable power-up phase, thereby improving reliability without significantly increasing total lock time.
2Speed
If the lock detector asserts lock signal immediately when phase alignment is detected, then response time is reduced, but false positive indications occur due to frequency instability
Solution Approach 1:
The patent implements preliminary action by introducing a time delay mechanism that operates immediately after phase alignment detection. The circuit performs the phase comparison quickly, but then waits for a predetermined period before asserting the final lock signal. This approach maintains fast response for detecting phase alignment while ensuring frequency stability before final lock indication, thus balancing speed and reliability.
Solution Approach 2:
The patent applies feedback by continuously monitoring both reference and feedback signals during the delay period. The lock detector circuit observes the ongoing phase relationship and frequency stability throughout the predetermined time period, using this continuous feedback to confirm that true lock condition has been achieved before asserting the lock signal, thereby preventing false positives.
3Measurement precision
If dual edge-triggered flip flops are used to detect both rising and falling edges, then phase alignment detection accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the phase detection function into separate rising edge detection and falling edge detection paths using dual edge-triggered flip flops. Each edge type is handled by dedicated circuitry that compares phases independently, then their results are combined. This segmentation improves measurement precision by capturing complete phase information while organizing complexity into manageable, modular segments rather than a monolithic complex circuit.
Data Source
AI summary
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.