PLL Duty Cycle Calibration Using Shared Phase Detection
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in accurately calibrating loop gain and duty cycle due to variations in process, voltage, and temperature (PVT), which can lead to suboptimal phase noise performance and increased power consumption.
Innovation Solution
The implementation of a PLL with a loop gain function that is a function of an input phase offset time, allowing for concurrent or simultaneous duty cycle and loop gain calibration using a shared phase detector, thereby reducing system complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate calibration circuits are used for duty cycle and loop gain calibration, then calibration accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines duty cycle calibration and loop gain calibration into a single unified calibration circuit that uses one phase detector to perform both calibration functions. The phase detector output is processed to extract both duty cycle error information and loop gain error information, eliminating the need for separate calibration circuits and reducing overall system complexity while maintaining calibration accuracy.
Solution Approach 2:
The unified calibration circuit is designed to perform multiple calibration functions simultaneously. The same phase detector and processing circuitry are used for both duty cycle calibration and loop gain calibration, making the calibration system universal and multi-functional rather than requiring dedicated separate circuits for each calibration task.
2Measurement precision
If multiple separate calibration circuits are implemented, then calibration precision is improved, but power consumption increases
Solution Approach 1:
The patent merges duty cycle calibration and loop gain calibration into a single power-efficient circuit that shares common components including the phase detector, delay element, and processing logic. This consolidation eliminates redundant power consumption that would occur with separate calibration circuits while maintaining the precision of both calibration functions.
3Measurement precision
If duty cycle calibration is performed using traditional methods, then duty cycle accuracy is improved, but system complexity and power consumption increase
Solution Approach 1:
The patent introduces a delay element as an intermediary component that delays the feedback signal by a predetermined amount. This delay element serves as a mediator that enables the phase detector to detect duty cycle errors by comparing the reference signal with the delayed feedback signal, providing a simple and elegant solution that avoids complex calibration mechanisms while maintaining duty cycle accuracy.
Data Source
AI summary
To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, the phase offset information for even clock instances and odd clock instances may be extracted.