Distributed Duty Cycle Correction in PLL Clock Trees
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Solution Overview
Problem
Existing lock loop circuits, such as PLL and DLL, face challenges in minimizing skew between an input clock and clock tree outputs, particularly in achieving a 50% duty cycle clock with minimal delay in clock tree and input clock paths, while maintaining stability of the main PLL loop.
Innovation Solution
Incorporating a distributed duty cycle correction loop that operates independently of the main PLL loop, with duty cycle adjustment only affecting the falling edge of the clock, allowing both loops to operate simultaneously without interference, using a 4-phase duty cycle detector and adjustment circuitry to generate and control voltage bias signals for precise duty cycle adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle correction is implemented in clock tree circuits, then duty cycle accuracy is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The duty cycle correction function is segmented into multiple independent correction circuits, each responsible for correcting the duty cycle of specific clock signals. This segmentation allows the system to achieve accurate duty cycle correction while keeping each individual correction circuit relatively simple and manageable.
Solution Approach 2:
The clock tree circuit performs self-correction of duty cycle through feedback mechanisms where the circuit monitors its own output and automatically adjusts its operation to maintain 50% duty cycle, reducing the need for complex external control circuitry.
2Manufacturing precision
If multiple correction loops operate simultaneously, then correction effectiveness is improved, but loop stability and interference between loops worsen
Solution Approach 1:
The correction system is divided into multiple independent correction loops, each handling specific clock signals separately. This segmentation allows simultaneous operation of multiple loops while preventing interference between them, as each loop operates independently on its designated signals.
Solution Approach 2:
Phase detection circuits serve as intermediaries that detect phase differences and generate control signals for the correction loops. These intermediary detection mechanisms enable multiple loops to operate simultaneously by providing independent feedback paths that prevent mutual interference while maintaining overall system stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures a 50% duty cycle clock at the clock tree output with minimized delay, maintaining PLL stability and allowing both loops to operate concurrently, thus reducing skew and optimizing clock tree performance.
Implementation Method 1
a first phase detection circuit of the plurality of phase detection circuits may be configured to detect a phase difference between the adjusted fourth clock signal and a fourth feedback clock signal
Implementation Method 2
using a 4-phase duty cycle detector and adjustment circuitry to generate and control voltage bias signals for precise duty cycle adjustment
Implementation Method 3
reduces skew between an input clock and a plurality of clock tree outputs
Data Source
AI summary
A system, method and circuits are described that pertain to locked loop circuits, distributed duty cycle correction loop circuitry. In some embodiments, the system and circuit may involve or be configured for coupling with lock loop circuitry such as phase locked loop (PLL) circuitry and/or a delay locked loop (DLL) circuitry. For example, one illustrative implementation may include or involve a phase locked loop (PLL) with distributed duty cycle correction loop/circuitry.