PLL Edge Alignment Circuit for Faster Low-Bandwidth Lock
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Solution Overview
Problem
Phase-locked loops (PLLs) experience long lock times, especially with low frequency input clocks and very low loop bandwidths, leading to large full scale requirements that result in circuit offsets and potential clipping, and require lengthy evaluation cycles for switching between input clocks, which can disrupt system performance.
Innovation Solution
The method involves detecting the edge of the input clock signal to align the edge of the feedback signal using an edge detect circuit and feedback divider, reducing the need for large full scale ranges and enabling faster lock times by initially aligning the feedback signal with the input clock signal, and using edge detect corrections to adjust the feedback divider for subsequent cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the loop bandwidth is kept low (e.g., milliHz range) to maintain stability, then the PLL stability is improved, but the locking time becomes extremely long (hours or days)
Solution Approach 1:
The patent applies preliminary action by using an edge detect circuit to identify the first edge of the input clock signal and then proactively adjusting the feedback divider to align the feedback signal edge with the input clock edge before the normal locking process begins. This preliminary alignment dramatically reduces the time required for the PLL to acquire lock, eliminating the need to wait hours or days for a low bandwidth PLL to naturally converge.
2Adaptability or versatility
If the full scale requirements are increased to handle large startup differences, then the circuit can accommodate larger phase/frequency differences, but circuit offsets increase due to process variations
Solution Approach 1:
The patent uses preliminary action by pre-aligning the feedback signal edge to match the input clock edge through the edge detect circuit and feedback divider adjustment. This eliminates large startup phase/frequency differences before they can cause clipping or require large full scale ranges, thereby maintaining measurement precision while still handling the expected signal variations.
Solution Approach 2:
The patent applies preliminary anti-action by preemptively correcting the feedback signal alignment using the edge detect circuit, thereby preventing the occurrence of large phase/frequency differences that would otherwise require large full scale ranges and cause clipping or non-linear responses in the PFD.
3Measurement precision
If the full scale requirements are reduced to decrease circuit offsets, then measurement accuracy improves, but clipping occurs when large phase/frequency differences are present
Solution Approach 1:
The patent applies preliminary action by using the edge detect circuit to identify the first edge and proactively adjusting the feedback divider to align edges before the PFD processes the signals. This prevents large phase/frequency differences from reaching the PFD, eliminating clipping while allowing the circuit to operate with smaller, more accurate full scale ranges.
Solution Approach 2:
The patent uses preliminary anti-action by preemptively preventing large phase/frequency differences from causing clipping through edge alignment. This allows the use of smaller full scale ranges that provide better measurement accuracy without risking clipping, as the edge alignment ensures signals remain within the linear operating range.
4Measurement precision
If long digital capture and computation cycles are used to evaluate new clock signals, then switching accuracy is improved, but system performance degrades due to frozen oscillator output
Solution Approach 1:
The patent applies preliminary action by pre-aligning the feedback signal edge to the input clock edge using the edge detect circuit and feedback divider. This creates a head start condition where the PLL is already close to lock when switching occurs, allowing much shorter evaluation cycles and reducing or eliminating the need to freeze the oscillator output during clock switches.
5Stability of the object's composition
If very low bandwidth filters are used to maintain stability, then filter stability is improved, but large phase/frequency corrections disrupt the filter operation
Solution Approach 1:
The patent applies preliminary action by pre-aligning the feedback signal edge to match the input clock edge before signals enter the low bandwidth filter. This eliminates large phase/frequency corrections that would otherwise disrupt the filter, allowing the very low bandwidth filter to maintain stability while still enabling rapid lock acquisition through the edge alignment mechanism.
Data Source
AI summary
A phase-locked loop uses an edge detect circuit to detect an edge of an input clock signal. The detected edge is used to digitally align an initial edge of the feedback signal with the input clock signal to the PLL so that the feedback signal is substantially aligned with the input clock signal. The edge alignment of the feedback signal may be performed at startup or in response to loss of lock/input clock switching. By aligning the feedback signal the input clock signal based on the edge detect, faster lock occurs.