Hybrid Phase-Locked Loop Error Filtering for Jitter Suppression
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Solution Overview
Problem
Phase locked loops (PLLs) produce synchronized clock signals but often suffer from noise, specifically jitter, which affects the accuracy and stability of the output signal, as it is generated by various components within the PLL device.
Innovation Solution
A system comprising a PLL device with a digital phase detector, a delay element, and a digital filter that determines and filters PLL error, such as jitter, from the output signal to produce a filtered signal for the analog phase detector, ensuring the output signal is locked to a reference signal with reduced noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop is used to produce synchronized clock signals, then the output signal is locked to a reference signal, but the output signal contains noise and jitter that affect accuracy and stability
Solution Approach 1:
The patent segments the PLL system into multiple independent components: an analog phase detector for coarse phase detection, a digital phase detector for precise error measurement, a delay element for signal timing adjustment, and a digital filter for noise removal. This segmentation allows each component to specialize in specific functions, improving overall signal quality while maintaining synchronization.
Solution Approach 2:
The patent introduces a digital filter as an intermediary component between the VCO and the analog phase detector. This digital filter acts as a mediator that removes jitter and noise from the feedback signal before it reaches the analog phase detector, preventing noise propagation while maintaining the locking function.
2Object-generated harmful factors
If traditional PLL components are used, then the system structure is simple, but the jitter and noise cannot be effectively filtered
Solution Approach 1:
The patent replaces traditional analog filtering mechanisms with a digital filter implementation. The digital filter uses digital signal processing techniques to remove jitter and noise, substituting complex analog circuitry with programmable digital logic that achieves superior noise rejection while maintaining system manageability.
Solution Approach 2:
The patent creates a hybrid PLL system that combines analog and digital components into a composite architecture. The analog phase detector handles coarse phase detection while the digital phase detector and digital filter handle precise error correction, creating a composite system that leverages the strengths of both analog and digital domains to achieve effective jitter suppression.
Data Source
AI summary
A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.