Fractional-N PLL Even/Odd Divider Compensation for Reference Spurs
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Solution Overview
Problem
Phase lock loops (PLLs) face issues with high-reference spurs and increased phase noise due to non-50% duty cycle reference clocks, which cause mismatches in even and odd clock periods, leading to uncorrelated noise and in-band noise increases.
Innovation Solution
A method and apparatus that determine the phase difference between even and odd cycles of a reference clock and feedback clock in a PLL, adjusting the division value used by a divider to generate the feedback clock based on delta values of alternating polarity to align the feedback clock with the reference clock, thereby reducing noise and tracking temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a reference clock doubler circuit is used to generate the reference clock, then the reference clock frequency is doubled, but the non-50% duty cycle causes mismatch between even and odd clock periods, leading to high-reference spurs and increased phase noise
Solution Approach 1:
The patent segments the feedback clock generation into even and odd cycles, applying different division values to each cycle type. This segmentation allows independent optimization of each cycle's feedback timing to compensate for the duty cycle mismatch caused by the reference clock doubler, thereby reducing reference spurs and phase noise while maintaining the doubled reference frequency.
Solution Approach 2:
The patent dynamically adjusts the feedback clock division value based on whether the current cycle is even or odd. By making the division value dynamic rather than static, the system can adapt to the alternating pattern of clock period mismatches, compensating for the duty cycle non-idealities and reducing the harmful effects on PLL performance.
2Manufacturing precision
If digital tuning is used to adjust the duty cycle of reference clock, then the duty cycle can be corrected, but large glitches are introduced to the output clock
Solution Approach 1:
The patent introduces an intermediary mechanism - the alternating even/odd cycle division value adjustment - that indirectly compensates for duty cycle mismatch without directly modifying the reference clock signal. This intermediary approach achieves duty cycle correction effects while avoiding the large glitches that would result from direct digital tuning of the reference clock.
3Manufacturing precision
If analog tuning is used to adjust the duty cycle of reference clock, then the duty cycle can be corrected, but noise is increased
Solution Approach 1:
The patent replaces the analog tuning mechanism with a digital approach that adjusts division values in the feedback path. This substitution eliminates the noise associated with analog tuning circuits while achieving the same duty cycle correction effect through digital logic that modifies the feedback clock timing based on even/odd cycle detection.
4Object-generated harmful factors
If the division value is adjusted to align feedback clock with reference clock, then reference spurs are reduced, but the system complexity increases
Solution Approach 1:
The patent applies local quality by making the division value specific to each cycle type (even or odd) rather than using a single global division value. This localized adjustment approach targets the specific problem areas where duty cycle mismatch occurs, reducing reference spurs effectively while keeping the overall system complexity manageable through a structured, predictable pattern of adjustment.
Data Source
AI summary
In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity.