PLL Fast-Lock Circuit to Avoid Cycle Slip at Startup
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Solution Overview
Problem
Traditional phase-locked loop circuits face prolonged locking times due to cycle slip, which occurs when the reference clock frequency is close to the feedback clock frequency, leading to increased locking time and power consumption when extra current is added to enhance loop bandwidth.
Innovation Solution
A fast lock phase-locked loop circuit that adjusts the initial output frequency of the voltage-controlled oscillator by modifying the initial control voltage and uses an intermediate circuit to disconnect and reconnect the loop during automatic frequency calibration, ensuring the reference clock phase leads or lags the feedback clock phase, thereby avoiding cycle slip without increasing power consumption or circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If extra current is added in the charge pump to increase loop bandwidth and reduce locking time, then locking time is reduced, but power consumption and circuit complexity increase
Solution Approach 1:
The patent applies preliminary action by pre-setting the initial control voltage of the VCO during the startup phase to ensure the feedback clock frequency is lower than the reference clock frequency. This preliminary frequency setting prevents cycle slip before it can occur, eliminating the need for extra charge pump current and associated power consumption increases.
Solution Approach 2:
The patent changes the parameter of initial control voltage to adjust the initial output frequency of the VCO. By modifying this voltage parameter during startup, the system creates a controlled frequency difference that prevents cycle slip, achieving fast locking without the power consumption penalty of increased charge pump current.
2Object-generated harmful factors
If reference clock frequency is very close to feedback clock frequency, then output noise is reduced, but locking time is greatly increased
Solution Approach 1:
The patent uses preliminary action by establishing a controlled frequency difference through initial control voltage adjustment during startup. This preliminary action ensures the feedback clock frequency is deliberately set lower than the reference clock frequency, creating sufficient phase change rate for fast locking while maintaining low output noise through proper frequency relationship management.
Solution Approach 2:
The patent applies dynamics by making the control voltage time-dependent - using a different initial control voltage during startup compared to normal operation. This dynamic adjustment allows the system to have different frequency relationships at different times: a controlled difference during startup for fast locking, and close frequencies during normal operation for low noise.
3Reliability
If initial output frequency of VCO is adjusted by modifying initial control voltage, then cycle slip is avoided, but circuit complexity increases
Solution Approach 1:
The patent changes the parameter of control voltage to achieve cycle slip avoidance. By adjusting the initial control voltage of the VCO during startup, the system creates a controlled frequency difference that prevents phase reversal. This parameter change approach uses existing circuit components with modified operating parameters, avoiding the need for additional circuitry.
Solution Approach 2:
The patent applies self-service by using the existing VCO and control voltage circuitry to solve the cycle slip problem. The system uses its own internal control voltage mechanism to adjust the initial frequency, rather than requiring external or additional components. This self-service approach maintains circuit simplicity while achieving reliability improvement.
Data Source
AI summary
Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started.