PLL Loop Filter Switching for Fast Lock and Low Noise
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Solution Overview
Problem
Existing PLL circuits face challenges in achieving desired performance due to difficulties in achieving fast locking and noise reduction while maintaining loop stability, particularly when using a BB-PD for phase detection.
Innovation Solution
The PLL circuit incorporates a lock detector that controls the gain of a cumulative adder and bandwidth of a filter based on lock state detection, switching between a first integral path for fast lock mode and a second integral path for normal mode, with a configuration including proportional, first integral, and second integral paths, along with a ΔΣ modulator and DACs, to achieve efficient locking and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a BB-PD is used for phase detection in a PLL circuit, then the phase detection capability is improved, but the lock time increases and noise increases
Solution Approach 1:
The integral path is divided into two separate paths: a first integral path with a first cumulative adder for fast locking, and a second integral path with a second cumulative adder for noise reduction. This segmentation allows each path to be optimized for its specific function, resolving the contradiction between fast locking and noise reduction while maintaining BB-PD phase detection capability
Solution Approach 2:
The gains of the first and second cumulative adders are made variable rather than fixed. The lock detector dynamically adjusts these gains based on the locking state, enabling the system to switch between fast-locking mode (high gain) and noise-reduction mode (low gain), thus resolving the time-loss contradiction
2Loss of time
If the gain of the cumulative adder is increased to achieve fast locking, then the lock time is reduced, but the noise increases
Solution Approach 1:
The integral path is divided into two separate paths: a first integral path with a first cumulative adder for fast locking, and a second integral path with a second cumulative adder for noise reduction. This segmentation allows each path to be optimized for its specific function, resolving the contradiction between fast locking and noise reduction
Solution Approach 2:
The gains of the first and second cumulative adders are dynamically adjusted based on the locking state detected by the lock detector, enabling the system to use high gain during fast-locking mode and low gain during normal operation to minimize noise
3Object-generated harmful factors
If the bandwidth of the filter is increased to reduce noise, then the noise reduction is improved, but the loop stability deteriorates
Solution Approach 1:
The integral path is divided into two separate paths with different filter configurations. The first filter in the fast-locking path has higher bandwidth for fast response, while the second filter in the noise-reduction path has lower bandwidth for better noise filtering, allowing both stability and noise reduction to be achieved simultaneously
Solution Approach 2:
The bandwidths of the first and second filters are dynamically adjusted based on the locking state. During fast locking, the first filter operates with higher bandwidth for quick response. After locking is achieved, the system switches to the second filter with lower bandwidth for noise reduction while maintaining loop stability
Data Source
AI summary
A PLL circuit having a desired performance is provided. A PLL circuit (100) includes a phase comparator (11) that detects a phase difference; a voltage control oscillator (12) that generates a signal to be returned to the phase comparator (11); and a loop filter (10) that is disposed between the phase comparator (11) and the voltage control oscillator (12) and includes an adder (50) that adds outputs from a proportional path (20), a first integral path (40), and a second integral path (30). The second integral path (30) and the first integral path (40) each include a cumulative adder, a ΔΣ modulator, and an RC filter. The lock detector (36) detects a lock state, controls a gain of the first cumulative adder (42) and a bandwidth of the first RC filter (45), and switches an input to a second ΔΣ modulator (33) to a fixed value.