PLL Pre-Programming for Fast Lock After Low-Power Reset
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Solution Overview
Problem
Phase locked loops (PLLs) in integrated circuits face significant delays when exiting a low power state, as they often need to re-lock to the previous frequency before locking to a new frequency, wasting time and causing operational delays.
Innovation Solution
A method and apparatus that allow a PLL to be programmed to lock directly to a new frequency upon exiting a low power state by maintaining the analog portion powered on and storing programmable parameters in registers, enabling direct transition to the new state without intermediate locking to the previous frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the PLL is powered down in low-power mode, then power consumption is reduced, but the lock time increases when exiting the low-power state
Solution Approach 1:
The PLL is divided into two independent segments: an analog portion that remains powered on during low-power mode and a digital portion that is powered down. This segmentation allows the analog portion to maintain frequency locking capability while the digital portion enters low-power state, enabling fast re-lock without requiring complete PLL re-initialization.
Solution Approach 2:
The analog portion of the PLL performs preliminary action by remaining active and maintaining frequency reference during low-power mode. This preliminary maintenance of frequency locking capability eliminates the need for complete re-locking when exiting low-power state, significantly reducing lock time.
2Stability of the object's composition
If the PLL re-locks to the previous frequency before locking to a new frequency, then frequency stability is maintained, but the operational delay increases
Solution Approach 1:
The digital portion is programmed with the new frequency parameters (divisors and multiplication factor) in advance while the PLL operates at the previous frequency. This preliminary programming eliminates the need for sequential frequency transitions, allowing direct transition to the new frequency upon exiting low-power state.
Solution Approach 2:
The system dynamically adjusts the locking behavior based on the exit from low-power state. Instead of following the fixed sequence of locking to previous frequency first then new frequency, the PLL dynamically transitions directly to the new frequency using pre-programmed parameters, reducing operational delay while maintaining frequency stability.
Data Source
AI summary
A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.