PLL Fast Settling Using Shortened VCO Calibration in TDD

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Solution Overview

Problem

Cellular phones face challenges in calibrating voltage-controlled oscillators (VCOs) within phase locked loops (PLLs) when transitioning between transmit and receive modes of operation, often within time constraints set by communications standards, leading to potential misalignment with the appropriate receive frequency.

Innovation Solution

A communications device with a controller module that performs a shortened calibration, such as fine or offset calibration, to quickly adjust the VCO's target signal, allowing it to lock onto the reference signal within the specified time frames, using a reference PLL with components like a phase/frequency detector, charge pump, loop filter, and voltage-controlled oscillator, and selecting the appropriate calibration method based on the communications standard.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If additional calibration of the VCO is performed when transitioning between transmit and receive modes, then frequency alignment accuracy is improved, but the time required for mode transition increases

Engineering Contradiction:
Improvefrequency alignment accuracyVSAvoidmode transition time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing calibration values for the VCO at different operating temperatures. When transitioning between transmit and receive modes, the system retrieves the pre-computed calibration value corresponding to the current temperature, eliminating the need for time-consuming real-time calibration. This allows the PLL to quickly adjust to the correct frequency without extending mode transition time, thus resolving the contradiction between calibration accuracy and transition speed.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If the VCO is calibrated to track the reference signal accurately, then receive frequency alignment is improved, but the settling time of the PLL increases

Engineering Contradiction:
Improvereceive frequency alignmentVSAvoidPLL settling time
Core Design Contradiction:
Measurement precisionVSDuration of action of moving object

Solution Approach 1:

The system pre-computes calibration values for the VCO at various temperatures and stores them in a lookup table. During operation, when temperature changes are detected, the system retrieves the appropriate pre-computed calibration value and applies it to the VCO control signal. This preliminary preparation of calibration data allows the PLL to achieve accurate frequency alignment without requiring extended settling time, as the calibration adjustments are already optimized and ready for immediate application.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter being controlled by the VCO from a fixed frequency to a temperature-compensated frequency. By monitoring temperature and selecting appropriate calibration values from pre-computed tables, the system dynamically adjusts the VCO's operating characteristics to maintain accurate frequency alignment across varying thermal conditions. This parameter change approach enables the PLL to achieve proper frequency tracking without requiring prolonged settling periods, as each temperature-specific calibration value is optimized for rapid convergence.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2590263B1Apparatus and method for fast Phase Locked Loop (PLL) settling for cellular Time-Division Duplex (TDD) communications system
Publication Date: 2018.09.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • EP2590263B1 patent drawingFigure 1
  • EP2590263B1 patent drawingFigure 2
  • EP2590263B1 patent drawingFigure 3

AI summary

A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation.