PLL Feedback Delay Circuit for Fast Lock Without Instability
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Solution Overview
Problem
Phase locked loops (PLLs) face challenges in reducing lock time while maintaining stability, as increasing loop gain can lead to increased lock time and instability, particularly in charge pump PLLs.
Innovation Solution
Incorporating a delay circuit between the N divider circuit and the phase detector in the feedback path of the PLL, which allows for increased loop gain to reduce lock time without causing instability, by adjusting the delay based on loop gain and reducing it after locking to minimize jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If loop gain is increased to reduce lock time, then lock time is reduced, but loop stability deteriorates
Solution Approach 1:
A delay circuit is introduced as an intermediary element in the feedback path between the N divider circuit and the phase detector. This delay circuit acts as a mediator that modifies the feedback signal timing to enable higher loop gain operation while maintaining loop stability. The delay circuit compensates for the destabilizing effect of high loop gain by adjusting the phase characteristics of the feedback path.
2Stability of the object's composition
If delay is increased to maintain stability with high loop gain, then loop stability is maintained, but lock time increases
Solution Approach 1:
The delay circuit is configured to dynamically adjust its delay amount based on the locking state of the PLL. During the acquisition phase before locking, the delay circuit provides a larger delay to enable high loop gain operation and fast locking. After locking is achieved, the delay circuit reduces its delay amount to minimize jitter and optimize steady-state performance. This dynamic adjustment resolves the contradiction between needing delay for stability and avoiding delay for fast locking.
3Stability of the object's composition
If delay circuit is added to enable high loop gain, then loop stability is maintained, but device complexity increases
Solution Approach 1:
The delay circuit is designed to perform multiple functions within the PLL system: (1) enabling high loop gain operation by compensating phase characteristics, (2) reducing lock time during acquisition, (3) minimizing jitter after locking through dynamic delay adjustment, and (4) maintaining loop stability. By consolidating these multiple functions into a single delay circuit component, the patent achieves the benefits of high loop gain and fast locking without proportionally increasing device complexity.
Data Source
AI summary
Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.