PLL Feedback Divider Architecture for Low Jitter Fractional Locking
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Solution Overview
Problem
Standard Phase Locked Loops (PLLs) face challenges in reducing output jitter, particularly due to noise generated by Sigma Delta Modulators, which is not effectively addressed by existing solutions that either reduce operating bandwidth or introduce instability.
Innovation Solution
Incorporating a fractional feedback divider and a second divider in series with a Sigma Delta Modulator to generate a modulated clock at a higher frequency, allowing the PLL to operate in both integer and fractional modes, and using a Multiplexer to select between divided and modulated clocks to minimize jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the loop filter bandwidth is increased to improve settling time, then the PLL locks faster, but the output becomes unstable at higher reference frequencies
Solution Approach 1:
The feedback divider is segmented into two independent stages: an integer divider and a fractional divider. The integer divider provides stable frequency division with fixed ratio, while the fractional divider implements dynamic modulation to achieve fractional division ratios. This segmentation allows the integer stage to maintain stability while the fractional stage provides the flexibility needed for fast locking without compromising overall system stability.
2Measurement precision
If the reference frequency is lowered to improve frequency resolution, then the PLL achieves finer tuning steps, but the settling time increases
Solution Approach 1:
The feedback divider ratio is transformed from a static integer value to a dynamic fractional value through the introduction of a fractional divider stage. This dynamic division ratio allows the PLL to achieve fine frequency resolution by adjusting the fractional component while maintaining a higher reference frequency, thereby reducing settling time without sacrificing frequency resolution.
3Measurement precision
If a Sigma Delta Modulator is used to improve tuning resolution in fractional PLLs, then fractional division ratios are achieved, but quantization noise is generated resulting in spurious tones
Solution Approach 1:
The harmful quantization noise generated by the Sigma Delta Modulator is extracted and directed to a dedicated noise output terminal separate from the main feedback path. By removing the noise component from the feedback loop, the spurious tones are eliminated while preserving the beneficial fractional division capability. The clean feedback signal continues to provide accurate frequency control without the contaminating noise.
4Measurement precision
If the PLL operates in fractional mode to improve tuning resolution, then finer frequency control is achieved, but jitter increases due to noise from the Sigma Delta Modulator
Solution Approach 1:
A dual-path architecture is introduced where the feedback signal travels through a clean integer divider path while the fractional modulation occurs in a separate path. The integer divider acts as an intermediary that provides a stable, noise-free feedback signal to the phase detector, while the fractional divider handles the modulation independently. This separation prevents jitter from propagating into the main feedback loop while still achieving fractional tuning resolution.
Data Source
AI summary
A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.