PLL Coarse-Fine Feedback Control for Faster Frequency Lock
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Solution Overview
Problem
Conventional phase locked loops (PLLs) suffer from slow settling time and large capacitor sizes due to their low bandwidth, coarse tuning loops, which limits their performance and desirability in certain systems.
Innovation Solution
A PLL design incorporating a voltage controlled oscillator (VCO) with a capacitive network, switched capacitor array, and a control loop that includes a bang-bang controller, precision lock detector, and window adjust circuits to provide additional discrete time controls and adjust capacitance for improved phase and frequency lock, reducing settling time and noise sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a low bandwidth, coarse tuning loop is used in conventional PLLs, then the tuning range is extended, but the settling time becomes slow
Solution Approach 1:
The patent segments the tuning function into two independent paths: a coarse tuning path using capacitor banks for wide frequency range adjustment, and a fine tuning path using a voltage-controlled capacitor for precise frequency control. This segmentation allows each path to be optimized independently, resolving the contradiction between wide tuning range and fast settling time.
Solution Approach 2:
The patent implements dynamic switching between coarse and fine tuning modes based on the locking state. During acquisition, the coarse tuning path is active for rapid frequency adjustment. Once locked, the system transitions to fine tuning mode for precise frequency control, enabling fast settling while maintaining accuracy.
2Object-generated harmful factors
If a large calibration capacitor is used to suppress amplifier noise, then the noise performance improves, but the device size increases
Solution Approach 1:
The patent replaces the traditional large analog calibration capacitor with a digitally controlled capacitor array. The digital control mechanism allows precise adjustment of capacitance values without requiring large physical capacitor sizes, achieving noise suppression through digital signal processing rather than large analog components.
Solution Approach 2:
The patent changes the capacitance parameter dynamically through digital control of the capacitor array. By switching between different capacitor combinations in the array, the system achieves variable capacitance values for noise suppression without requiring a single large fixed capacitor, thereby reducing overall device size.
3Adaptability or versatility
If continuous calibration is applied to extend tuning range, then the frequency coverage increases, but the settling time increases
Solution Approach 1:
The patent applies preliminary coarse tuning to quickly bring the VCO frequency close to the target frequency before engaging the fine tuning mechanism. This preliminary action covers the majority of the frequency range adjustment, allowing the subsequent fine tuning to complete the adjustment rapidly, thereby achieving wide frequency coverage without proportionally increasing settling time.
4Adaptability or versatility
If a wide tuning bandwidth is implemented, then the frequency range increases, but the phase noise performance deteriorates
Solution Approach 1:
The patent segments the tuning bandwidth into coarse and fine components. The coarse tuning path provides wide frequency range with minimal impact on phase noise, while the fine tuning path operates with narrow bandwidth to maintain excellent phase noise performance. This segmentation allows the system to achieve wide overall tuning range while preserving low phase noise through the fine tuning path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances PLL performance by reducing settling time, improving phase noise, and decreasing sensitivity to parasites, while allowing for a reduced analog tuning range and lower VCO current, thus offering better noise performance compared to conventional PLLs.
Implementation Method 1
a capacitive network that receives a first tuning voltage; and a switched capacitor array that is coupled to the capacitive network
Implementation Method 2
an amplifier that receives the first tuning voltage and a reference voltage, wherein the amplifier amplifies the difference between the reference voltage and the first tuning voltage
Implementation Method 3
a control loop that receives the input signal and the second tuning voltage, wherein the controller loop controls the switch so as to apply the reference voltage to the calibration capacitor when the apparatus resets, and wherein the control loop controls the switched capacitor array so as to adjust the capacitance of the VCO to generally maintain phase and frequency lock
Data Source
AI summary
An apparatus is provided. The apparatus comprising a voltage controlled oscillator (VCO), an amplifier, a switch, a calibration capacitor, and a control loop. The VCO includes a capacitive network that receives a first tuning voltage that is based at least in part on an input signal and a switched capacitor array that is coupled to the capacitive network. The amplifier amplifies the difference between the reference voltage and the first tuning voltage. The switch receives the reference voltage and the amplified difference between the reference voltage and the first tuning voltage. The calibration capacitor receives the output from the switch and generates a second tuning voltage. The control loop receives the input signal and the second tuning voltage. The control loop also controls the switch so as to apply the reference voltage to the calibration capacitor when the apparatus resets and controls the switched capacitor array so as to adjust the capacitance of the VCO to generally maintain phase and frequency lock.