PLL Delay Circuit Outside the Feedback Loop for Stable Output
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Solution Overview
Problem
Conventional PLL circuits experience increased jitter due to overlapping power-supply noise and phase comparison timing, which destabilizes the output signal, particularly in semiconductor IC devices with both analog and digital circuits.
Innovation Solution
A PLL circuit design that includes a phase comparator, an oscillator, a feedback loop, and a delay circuit positioned outside the feedback loop, where the delay circuit automatically adjusts its delay time based on the output signal's frequency, ensuring the power-supply noise does not overlap with the phase comparison timing, thereby suppressing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay circuit is placed inside the feedback loop to adjust phase timing, then the jitter can be suppressed, but the lock-up speed is reduced and circuit complexity increases
Solution Approach 1:
The delay circuit is extracted from the feedback loop and placed outside it, specifically between the oscillator and the digital circuit. This extraction allows the delay function to be maintained for jitter suppression while preventing the delay from affecting the feedback timing and lock-up speed.
Solution Approach 2:
The delay circuit acts as an intermediary element positioned between the oscillator output and the digital circuit input. It mediates the signal transmission by introducing controlled delay only where needed, without interfering with the feedback path that determines lock-up speed.
2Reliability
If a phase shifter with delay length switching portion is used to reduce jitter, then the signal stability improves, but the device complexity and circuit size increase
Solution Approach 1:
The delay circuit automatically adjusts its delay characteristic based on the output signal frequency without requiring external control or switching mechanisms. The circuit self-regulates to provide optimal delay for jitter suppression across different operating conditions.
Solution Approach 2:
The delay circuit is designed to function universally across different frequency ranges and operating conditions without requiring additional switching components or complex control logic. A single delay circuit structure handles multiple functions that would otherwise require separate components.
3Device complexity
If the power-supply noise overlaps with phase comparison timing, then the circuit operation is simplified, but the output signal becomes destabilized due to jitter
Solution Approach 1:
The delay circuit is positioned to preemptively separate the power-supply noise timing from the phase comparison timing before the comparison occurs. By introducing delay in advance, the circuit prevents the harmful overlap from occurring in the first place.
Solution Approach 2:
The delay circuit converts the potentially harmful effect of power-supply noise by timing it to occur outside the critical phase comparison window. The same noise that could destabilize the system is effectively isolated from the sensitive comparison operation through strategic timing arrangement.
Data Source
AI summary
A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.