PLL Feedback Multiplexing for Fine Phase Offset and Low Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic divider PLL devices face issues with phase noise and jitter due to the switching of division ratios, which causes quantization noise, especially in high-performance applications requiring low jitter levels.
Innovation Solution
The implementation of a feedback portion with multiple instances of phase and frequency detectors and charge pumps, along with a multiplex network, allows for finer temporal resolution of phase changes within one clock cycle, reducing quantization noise by generating multiple feedback clock signals that collectively provide feedback for phase/frequency comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dynamic divider is used to achieve fractional-N PLL functionality with flexible frequency synthesis, then adaptability and versatility are improved, but phase noise and jitter increase due to quantization noise from division ratio switching
Solution Approach 1:
The feedback path is segmented into multiple parallel PFD/CP instances (first, second, and third instances), each receiving a different feedback clock signal (first, second, and third feedback clock signals). This segmentation allows the system to distribute the quantization noise across multiple channels and combine their outputs, thereby reducing the overall phase noise and jitter while maintaining the adaptability of fractional-N PLL frequency synthesis
Solution Approach 2:
A multiplex network is introduced as an intermediary component that selectively routes different feedback clock signals to different PFD/CP instances based on control signals. This multiplex network enables dynamic switching between different feedback paths, allowing the system to optimize performance by selecting appropriate feedback signals for different operating conditions, thus reducing quantization noise while maintaining frequency synthesis flexibility
2Object-generated harmful factors
If multiple feedback clock signals are generated and processed through multiple PFD/CP instances, then phase noise and jitter are reduced, but device complexity increases
Solution Approach 1:
Multiple PFD/CP instances are designed with identical functional structures, where each instance performs the same phase detection and charge pumping operations but with different feedback clock signals. This universal design allows the system to reduce phase noise through parallel processing while minimizing the increase in device complexity, as each instance can be implemented using the same standardized circuit block
Solution Approach 2:
The outputs of multiple PFD/CP instances are merged and combined through a summation node to produce a single composite output signal. This merging approach consolidates the benefits of multiple parallel processing paths into a single unified output, reducing phase noise and jitter while avoiding the need for separate output circuits for each instance, thereby limiting the increase in device complexity
Data Source
AI summary
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.