PLL Feedback Multiplexing for Multi-Cycle Phase Interpolator Settling
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Solution Overview
Problem
Traditional phase lock loop (PLL) circuits face challenges in achieving sufficient phase shift settling time within a single clock cycle, leading to potential errors and increased power consumption due to the need for fast phase interpolators, which also generate extra pulse edges and glitches.
Innovation Solution
The implementation of multiple phase interpolators with a selection module and multiplexer in the PLL circuit allows for increased settling time and reduced bandwidth and power consumption by enabling phase jumps across multiple clock cycles, with one phase interpolator settling before the next reference clock edge, thereby minimizing glitches and pulse edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single phase interpolator is used to achieve fast phase shifting, then phase shift speed is improved, but settling time is insufficient and glitches increase
Solution Approach 1:
The single phase interpolator is segmented into multiple phase interpolators (first phase interpolator and second phase interpolator) that operate at different speeds. The first phase interpolator operates at a higher speed for rapid phase adjustment, while the second phase interpolator operates at a lower speed for stable settling, eliminating the need to choose between speed and reliability.
Solution Approach 2:
The system dynamically switches between different phase interpolators based on operational requirements. A selection module multiplexes the outputs of multiple phase interpolators, allowing the circuit to transition from fast phase shifting to stable settling by selecting appropriate interpolator outputs at different times.
2Reliability
If phase interpolator bandwidth is increased to reduce settling time, then settling time is improved, but power consumption increases
Solution Approach 1:
The phase interpolator function is segmented into multiple interpolators with different bandwidths and power consumption characteristics. The first phase interpolator has higher bandwidth and consumes more power for fast settling, while the second phase interpolator has lower bandwidth and consumes less power for maintenance operation, allowing the system to achieve fast settling without continuously consuming high power.
Solution Approach 2:
The system uses periodic switching between phase interpolators based on settling requirements. During initial phase jumps, the high-bandwidth interpolator is activated; after settling is achieved, switching occurs to the low-bandwidth interpolator, creating a periodic action pattern that reduces average power consumption while maintaining settling performance.
3Speed
If phase jumps occur within a single clock cycle, then phase shift speed is improved, but errors and glitches increase
Solution Approach 1:
The phase jumping process is segmented across multiple clock cycles using multiple phase interpolators. Instead of completing the entire phase jump in one clock cycle which causes glitches, the system divides the phase adjustment into stages, with each interpolator handling a portion of the transition, thereby reducing harmful transient effects.
Solution Approach 2:
The system performs preliminary phase adjustment using the first phase interpolator before final settling with the second phase interpolator. This preliminary action allows the majority of the phase jump to occur in a controlled manner, with subsequent fine-adjustment that minimizes glitches and pulse edges.
Data Source
AI summary
A phase lock loop circuit includes a phase frequency detector, a voltage controlled oscillator, a phase interpolator, a clock signal selector, a selection module, a multiplexer, and a divider. The phase frequency detector compares phases of a reference clock and frequency divided output signals and generates an error signal. The voltage controlled oscillator, based on the error signal, generates a phase lock loop output signal and output clock signals. The phase interpolator phase interpolates the output clock signals to generate an interpolator output signal. The clock signal selector selects one of the output clock signals. The selection module generates a selection signal based on states of the interpolator output and selected output clock signals. The multiplexer, based on the selection signal, selects the interpolator output signal or the selected output clock signal. The divider frequency divides an output of the multiplexer to provide the frequency divided output signal.