PLL Feedforward Circuit for Low-Noise VCO Phase Correction

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Solution Overview

Problem

Phase-locked loops (PLLs) suffer from phase noise due to imperfections in components like the voltage-controlled oscillator, charge pump, and loop filter, which worsens with miniaturization efforts.

Innovation Solution

The introduction of a direct feedforward circuit connected to the phase detector of a PLL, which applies an averaged version of the error signal to correct the voltage level received by the voltage-controlled oscillator, thereby reducing phase noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If miniaturization efforts are applied to PLL components, then device size is reduced, but phase noise increases

Engineering Contradiction:
ImprovePLL device sizeVSAvoidphase noise
Core Design Contradiction:
Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The error signal processing is segmented into two independent paths: a conventional feedback path through the charge pump and loop filter, and a new direct feedforward path that averages the error signal and applies it directly to the VCO. This segmentation allows the direct correction path to compensate for miniaturization-induced phase noise without requiring larger traditional filtering components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An averaging circuit is introduced as an intermediary component in the feedforward path. This intermediary processes the error signal to extract DC components and average variations, then applies this corrected signal directly to the VCO, thereby mediating the correction of phase noise without requiring large traditional filtering components.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If traditional loop filter design is used, then phase noise is filtered, but device complexity and size increase

Engineering Contradiction:
Improvephase noiseVSAvoidloop filter complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The harmful DC components and low-frequency variations are extracted from the error signal through the averaging circuit in the feedforward path. By removing these problematic components directly at the error signal stage and applying the corrected signal to the VCO, the patent eliminates the need for complex traditional loop filters that would otherwise be required to achieve the same noise filtering effect.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The averaging circuit performs preliminary correction of the error signal by averaging it over time to extract and eliminate DC components before the signal reaches the VCO. This preliminary action prevents phase noise from being introduced in the first place, rather than requiring complex post-processing filtering.

Inventive Principle:
Principle #10Preliminary action

3Object-generated harmful factors

If direct feedforward circuit is added, then phase noise is reduced, but circuit complexity increases

Engineering Contradiction:
Improvephase noiseVSAvoidcircuit complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

Rather than redesigning the entire PLL circuit, the invention applies a localized feedforward correction path that specifically targets the phase noise issue. The averaging circuit and direct feedforward connection are added only where needed - at the error signal input and VCO input - leaving the rest of the conventional PLL architecture intact, thus minimizing overall circuit complexity increase.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3895319B1Phase-locked loop (PLL) with direct feedforward circuit
Publication Date: 2025.06.11 TEXAS INSTRUMENTS INC
  • EP3895319B1 patent drawingFigure 1
  • EP3895319B1 patent drawingFigure 2
  • EP3895319B1 patent drawingFigure 3

AI summary

A phase-locked loop (PLL) device (102 A) includes: 1) a detector (104 A) configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump (106 A) coupled to the detector (104 A) and configured to output a charge pump signal based on the error signal; 3) an integrator (108 A) with a feedback path (202), an input node (109 A), a reference node (111 A), and an output node, wherein the input node (109 A) is coupled to the charge pump (106 A) and receives the charge pump signal; 4) a voltage-controlled oscillator (112A) coupled to the output node of the integrator (108 A) via a resistor; and 5) a feedforward circuit (110 A) coupled directly to the detector (104) A and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO (112A).