PLL Loop Filter With DC Level Shift for Low-Voltage NMOS Operation
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Solution Overview
Problem
Low supply voltage applications face challenges with phase-locked loop (PLL) circuits due to the inability of NMOS source followers to operate effectively, resulting in a low all-band power supply rejection ratio (PSRR) issue, as they require higher voltages to turn on.
Innovation Solution
A filter circuit with direct current (DC) level shift and a phase-locked loop (PLL) circuit design that includes a loop filter with a DC level shift circuit, allowing the NMOS source follower to operate under low supply voltage by deriving control voltages from both alternating current (AC) and DC components, ensuring high PSRR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS source follower is used to achieve high all-band PSRR, then power supply rejection ratio is improved, but the circuit cannot operate under low supply voltage
Solution Approach 1:
The control voltage is segmented into AC component and DC component, processed through separate paths. The AC component passes through capacitor C1 directly to the VCO gate, while the DC component goes through the level shift circuit (capacitors C5, C6 and switches SW1-SW5) to add the offset voltage. This segmentation allows each path to be optimized independently for its specific function.
Solution Approach 2:
The level shift circuit acts as an intermediary between the loop filter output and the VCO gate. It introduces an intermediate voltage node that accumulates charge on capacitor C6, which then provides the necessary DC offset to the VCO gate through switch SW5. This intermediary mechanism enables the VCO to operate at appropriate voltage levels even when the supply voltage is low.
2Use of energy by moving object
If low supply voltage is used for power saving, then power consumption is reduced, but NMOS source follower cannot turn on properly
Solution Approach 1:
The level shift circuit performs preliminary action by pre-charging capacitor C6 to the required offset voltage level before the VCO needs to operate. The switches SW1-SW4 are used to charge C6 in advance during specific phases, ensuring that when the VCO gate needs the DC control voltage, the offset is already prepared and available, enabling proper NMOS turn-on without requiring high supply voltage.
Solution Approach 2:
The circuit changes the voltage parameter at the VCO gate by adding a DC offset through the level shift mechanism. Instead of relying on the raw loop filter output voltage, the system actively modifies the DC level parameter by charging capacitor C6 to a specific voltage level and transferring it to the VCO gate, thereby ensuring the gate voltage remains within the required range for NMOS operation even under low supply conditions.
Data Source
AI summary
A filter includes a filter circuit, a first processing circuit, and a second processing circuit. The filter circuit receives an input signal from an input node of the filter, and converts the input signal into a voltage output. The first processing circuit provides a first control voltage to an output node of the filter according to the voltage output, wherein the first control voltage is derived from an alternating current (AC) component of the voltage output. The second processing circuit provides a second control voltage to the output node of the filter according to the voltage output, wherein the second control voltage is derived from applying DC level shift to a direct current (DC) component of the voltage output.