Modified PLL Loop Filter for Gain Peaking Compensation
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Solution Overview
Problem
Multi-loop phase locked loop (PLL) systems experience gain peaking due to the placement of a PLL inside the feedback loop, leading to undesirable transfer functions and increased gain, which complicates timing recovery and requires complex data interfaces in hierarchical timing networks.
Innovation Solution
A modified PLL system with a loop filter comprising a proportional path, an integral path, and an additional differential path, which combines signals to compensate for gain peaking, effectively mimicking a single PLL system's transfer function by adjusting coefficients to match the bandwidth and damping factor of a cascaded PLL system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLL is placed inside the feedback loop of another PLL in a hierarchical timing network, then timing recovery flexibility and network adaptability are improved, but gain peaking occurs leading to increased system complexity and undesirable transfer functions
Solution Approach 1:
The patent implements a nested PLL configuration where a first PLL is placed inside the feedback loop of a second PLL, creating a hierarchical timing network structure. This nesting enables flexible timing recovery while the additional functional path compensates for gain peaking effects, resolving the contradiction between adaptability and complexity
Solution Approach 2:
The patent employs feedback mechanisms through the nested PLL structure where the inner PLL's output feeds into the outer PLL's feedback path. This feedback arrangement provides adaptive timing recovery capability while the loop filter design compensates for potential instability and gain peaking
2Reliability
If a PLL is placed inside the feedback loop of another PLL, then clock synchronization capability is improved, but gain peaking increases requiring complex data interfaces
Solution Approach 1:
The patent converts the harmful gain peaking effect into a beneficial compensation mechanism by adding an additional functional path that specifically targets and counteracts the gain peaking. The harmful effect of gain peaking in the nested PLL structure is transformed into an opportunity to enhance synchronization reliability through targeted compensation
Solution Approach 2:
The patent modifies the loop filter transfer function by adding an additional functional path with specific parameters designed to compensate for gain peaking. By adjusting the coefficients and characteristics of this additional path, the system optimizes the transfer function to eliminate harmful gain peaking while maintaining synchronization capability
3Object-generated harmful factors
If a modified loop filter with additional functional path is added to compensate for gain peaking, then gain peaking is reduced and timing recovery is simplified, but device complexity increases
Solution Approach 1:
The patent segments the loop filter into distinct functional paths: a proportional path, an integral path, and an additional functional path. This segmentation allows each path to be optimized independently for its specific function while working together to compensate for gain peaking, making the overall complex filter more manageable and implementable
Data Source
AI summary
A loop filter in a modified phase locked loop has a proportional path generating first output signal that is proportional to an input signal and an integral path for generating a second output signal that is an integral of the input signal. An additional functional path generates a third output signal that is a predetermined function of the input signal. The predetermined function is of the form f(s)/g(s), where f and g are polynomial functions. An adder combines the first, second, and third output signals into a common output signal.