PLL Loop Filter Switching for Variable Coefficients in Less Chip Area
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Solution Overview
Problem
In large-scale integrated circuits (LSI), there is a need to reduce chip area while maintaining a variable filter coefficient in phase locked loop (PLL) circuits, as existing configurations are inefficient in terms of space utilization.
Innovation Solution
A phase locked loop circuit is designed with a loop filter comprising a first resistor, a first capacitor, a first switch, and a second capacitor, where the switch is controlled to generate a control voltage based on phase comparison results, allowing for a compact configuration with adjustable filter characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a loop filter is configured to have a variable filter coefficient, then the PLL circuit can alter its response characteristics and stability, but the chip area increases
Solution Approach 1:
The patent combines multiple filter coefficient configurations into a single loop filter structure by using switch elements to selectively connect different capacitor banks (C1, C2, C3) and resistor configurations. This merging approach allows the PLL to achieve variable filter characteristics without requiring separate physical loop filters for each configuration, thereby reducing overall chip area while maintaining adaptability.
Solution Approach 2:
The patent implements dynamic reconfiguration of the loop filter by introducing control signals that dynamically switch between different filter coefficient settings during operation. The switch elements (SW1, SW2, SW3) are controlled to connect or disconnect specific capacitors and resistors, enabling the filter characteristics to be dynamically adjusted based on operational requirements without permanently fixing the circuit topology.
2Adaptability or versatility
If multiple loop filters are provided for variable characteristics, then adaptability is improved, but device complexity increases
Solution Approach 1:
Instead of providing multiple separate loop filters, the patent merges multiple filter configurations into a single loop filter by using switch-controlled capacitor banks and resistor networks. The same physical capacitors (C1, C2, C3) and resistors are reused across different configurations, controlled by switch elements that connect them in different arrangements based on the desired filter characteristics.
Solution Approach 2:
The loop filter components (capacitors C1, C2, C3 and resistors R1, R2, R3) are designed to serve multiple functions across different operating modes. The same physical components can be connected in series or parallel configurations depending on the switch states, allowing a single set of components to provide multiple filter coefficient settings rather than requiring dedicated components for each setting.
Data Source
AI summary
Provided is a phase locked loop circuit that includes: a phase comparison section configured to compare a phase of a first clock signal and a phase of a second clock signal; a loop filter configured to generate a control voltage based on a comparison result by the phase comparison section; and a clock signal generation section configured to generate a clock signal having a frequency corresponding to the control voltage, and output the clock signal as the second clock signal. The loop filter includes a first resistor inserted between a first node on a signal path and a second node, a first capacitor inserted between the second node and a first DC power supply, a first switch inserted between the second node and a third node on the signal path, and a second capacitor inserted between the third node and a second DC power supply.