PLL Filter Circuit Using Thick Oxide Switches to Cut Clock Feed-Through
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Solution Overview
Problem
Conventional Phase Locked Loops (PLLs) experience significant clock feed-through issues, leading to noise and instability in the control voltage generated for voltage controlled oscillators (VCOs), which affects the stability and frequency accuracy of the output signal.
Innovation Solution
A system and method that utilize a filter comprising switching elements clocked via a clock booster circuit and thick oxide transistors to reduce clock feed-through, incorporating a sample and hold circuit with reset functionality, and a clock booster circuit to generate a control voltage for the VCO, thereby minimizing noise and instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switching elements are used in the PLL filter, then the device complexity is reduced, but clock feed-through causes noise and instability in the control voltage
Solution Approach 1:
The patent changes the physical parameter of the transistor by using thick oxide transistors instead of conventional thin oxide transistors. The thick oxide layer reduces the clock feed-through effect by providing better electrical isolation between the gate and channel, thereby reducing noise in the control voltage while maintaining switching functionality.
Solution Approach 2:
The patent introduces a clock booster circuit as an intermediary component between the clock signal source and the switching elements. This booster circuit conditions the clock signal to reduce direct coupling of clock feed-through to the control voltage node, acting as a mediator that isolates the harmful effect while maintaining clocking functionality.
2Object-affected harmful factors
If thick oxide transistors are used to reduce clock feed-through, then noise is reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent modifies the oxide thickness parameter of the transistor gate dielectric from conventional thin oxide to thick oxide. This parameter change reduces clock feed-through noise while utilizing standard CMOS fabrication processes, thereby managing manufacturing complexity through a well-established process variation rather than requiring entirely new fabrication techniques.
3Speed
If a clock booster circuit is added to clock the switching elements, then switching performance is improved, but the device complexity increases
Solution Approach 1:
The clock booster circuit serves as an intermediary stage that receives the base clock signal and transforms it into a boosted clock signal with improved voltage levels and edge characteristics. This intermediary circuit enhances switching speed performance while keeping the overall architecture manageable by performing a single, well-defined function of clock signal conditioning.
Data Source
AI summary
Aspects of a method and system for reduced clock feed-through in a phase locked loop are provided. In this regard, a control voltage for controlling a VCO may be generated via a filter comprising at least one switching element clocked via a clock booster circuit and comprising one or more thick oxide transistors to reduce clock feed-through. A first switching element of the filter may be a first transmission gate comprising thick oxide transistors. The first transmission gate may be part of a sample and hold circuit. A DC voltage on an input node of the sample and hold circuit may be periodically reset via a reset switching element, which may comprise thick oxide transistors. The reset switching element may be controlled via a clock booster circuit. The filter may also comprise a buffer having an input stage comprising one or more thick oxide transistors.