Programmable Fine Lock Detection for PLL Phase Error Monitoring
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Solution Overview
Problem
Existing feedback controlled clock generating circuits, such as PLL and DLL, face limitations in accurately detecting lock and unlock conditions due to coarse directional change detection, which makes it difficult to determine the cause of clock unlock, whether due to frequency or phase errors.
Innovation Solution
A programmable fine lock/unlock detection circuit with programmable static phase error sensitivity logic is introduced, allowing for a phase lock sensitivity window to be set, enabling fine phase lock/unlock signal generation and distinguishing between phase and frequency changes, thereby improving lock/unlock detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If coarse frequency based lock and unlock detection is used, then the device complexity is reduced, but the measurement precision of lock/unlock detection deteriorates
Solution Approach 1:
The detection circuit is segmented into two independent detection paths: a coarse frequency-based detection path using counters 208 and 210, and a fine phase-based detection path using programmable static phase error sensitivity logic 402. Each path handles different aspects of lock/unlock detection, allowing the system to achieve high precision without requiring a complete redesign of the entire detection circuit.
Solution Approach 2:
The invention adds a new dimension of phase-based detection to the existing frequency-based detection system. By introducing programmable static phase error sensitivity logic that operates in parallel with the frequency counters, the system transitions from one-dimensional frequency monitoring to two-dimensional monitoring that includes both frequency and phase dimensions, thereby improving overall detection precision.
2Device complexity
If coarse frequency based detection is used, then the device complexity is reduced, but the reliability of clock signal monitoring deteriorates
Solution Approach 1:
The monitoring function is segmented between coarse frequency monitoring (counters 208, 210) and fine phase monitoring (programmable static phase error sensitivity logic 402). This segmentation allows each subsystem to specialize in its detection domain, improving overall reliability without requiring a single complex monitoring system.
Solution Approach 2:
The programmable fine lock/unlock detection logic 402 provides enhanced feedback about phase errors to the core logic 112, enabling more reliable determination of whether the PLL is truly locked. The ability to programmably adjust phase error sensitivity allows the system to adapt feedback thresholds based on operational conditions, improving reliability.
3Measurement precision
If programmable fine lock/unlock detection logic is added, then the measurement precision of phase error detection is improved, but the device complexity increases
Solution Approach 1:
The programmable static phase error sensitivity logic 402 is designed as a universal block that can be configured through programmable registers to perform multiple detection functions. The same hardware structure can detect different phase error thresholds by loading different values into the programmable counters, eliminating the need for multiple dedicated detection circuits for different phase error conditions.
Solution Approach 2:
The detection precision is improved by making the phase error sensitivity programmable rather than fixed. By allowing the counter thresholds and sensitivity parameters to be changed through software configuration, the system achieves high measurement precision without requiring complex hardware for each possible detection threshold.
4Reliability
If fine phase lock sensitivity window is set, then the reliability of lock detection is improved, but the difficulty of detecting and measuring phase errors increases
Solution Approach 1:
The programmable static phase error sensitivity logic 402 is designed to automatically compare the phase of feedback signal against the reference signal within the programmable sensitivity window, eliminating the need for external complex measurement equipment. The circuit self-performs the phase error detection and generates lock/unlock indicators autonomously.
Data Source
AI summary
An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition.