PLL First-Cycle Divider Setting for Initial Phase Error Removal
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in reducing the initial phase error, which prolongs the locking time, especially in type-I PLLs where the target locking phase is non-zero, limiting their efficiency in communication systems.
Innovation Solution
The solution involves selectively controlling the feedback divider division value during the first division cycle to set the initial phase error to zero by configuring the division value as N*=N·ΔΦLCK/360, where N is the nominal division value, ensuring the phase relationship between the reference and feedback signals is immediately achieved, thus reducing the locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the PLL uses a conventional feedback divider with nominal division value N, then the PLL operates with standard locking characteristics, but the initial phase error is non-zero which prolongs the locking time
Solution Approach 1:
The patent applies preliminary action by pre-calculating and setting the division value to N* = N·ΔΦLCK/360 before the first division cycle begins. This preliminary configuration ensures that the feedback signal arrives at the phase detector with the correct phase relationship from the very first cycle, eliminating the initial phase error that would otherwise require time to correct through the feedback loop.
Solution Approach 2:
The patent changes the division value parameter from the nominal N to a modified value N* = N·ΔΦLCK/360 for the first division cycle. This parameter modification directly compensates for the non-zero target locking phase ΔΦLCK, allowing the PLL to achieve the correct phase relationship immediately rather than requiring time to converge to the locked state.
2Loss of time
If the PLL bandwidth is increased to reduce locking time, then the locking time decreases, but noise and spurs increase
Solution Approach 1:
By pre-configuring the division value to N* before the first division cycle, the patent achieves immediate phase alignment without requiring high bandwidth for rapid correction. This eliminates the need to increase bandwidth, thereby avoiding the associated increase in noise and spurs while still achieving fast locking.
3Reliability
If the PLL type is increased beyond type-I to achieve better locking performance, then the locking characteristics improve, but the device complexity increases
Solution Approach 1:
The patent maintains a simple type-I PLL architecture but changes the division value parameter to N* = N·ΔΦLCK/360. This parameter modification achieves the locking performance benefits of more complex PLL types without adding integrators or increasing device complexity, keeping the PLL architecture simple while improving locking characteristics.
Data Source
AI summary
Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.