PLL/FLL Clock Glitch Detection for Secure Off-Chip Timing
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Solution Overview
Problem
Contemporary electronic systems, such as data center devices and IoT devices, are vulnerable to hacking due to manipulation of the off-chip system clock, which can cause timing errors and allow unauthorized access to protected data, as hackers can inject faults like glitches into the system clock.
Innovation Solution
An on-die frequency-locked loop (FLL)-based or phase-locked loop (PLL)-based clock glitch detection device is employed to securely monitor the system clock, generating multiple local clocks and oversampling to detect glitches with high accuracy, reducing sensitivity to supply voltage variations and PVT corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the system uses an off-chip system clock, then the IC chip can operate with a standardized clock source, but the system becomes vulnerable to clock glitch attacks that can flip internal state bits and compromise security
Solution Approach 1:
The patent introduces an intermediary clock monitoring circuit that sits between the off-chip system clock and the IC chip's internal logic. This intermediary continuously monitors the clock signal for glitches and blocks or alerts on detected anomalies, thereby maintaining compatibility with standardized clock sources while protecting against glitch attacks.
Solution Approach 2:
The patent implements preliminary detection of clock glitches before they can affect the IC chip's internal state. By using a monitoring circuit that continuously checks the clock signal in advance, the system can identify and respond to potential attacks before they compromise security-critical operations.
2Stability of the object's composition
If the IC chip generates a local clock derived from the off-chip system clock, then timing synchronization is maintained, but the clock generation process becomes susceptible to fault injection and timing errors
Solution Approach 1:
The patent employs feedback mechanisms in the local clock generation circuitry, where the generated clock is continuously monitored and compared against expected characteristics. Any deviations or anomalies trigger corrective actions or alerts, ensuring that timing synchronization is maintained while protecting against fault injection attacks on the clock generation process.
3Measurement precision
If the system increases monitoring of the system clock for security, then detection accuracy improves, but current consumption increases
Solution Approach 1:
The patent implements partial monitoring by focusing detection resources on critical clock signal characteristics and time periods rather than continuously monitoring all aspects of the clock signal. This approach maintains high detection accuracy for security-critical glitches while reducing overall current consumption by avoiding excessive monitoring of non-critical parameters.
Data Source
AI summary
A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.