PLL-Free Synchronization Circuit for Switching Regulators
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Solution Overview
Problem
Existing synchronization circuits for switching regulators are costly and occupy large die area due to the use of Phase-Locked Loops (PLLs), which also experience stabilization time issues when transitioning between internal and external clock modes, leading to voltage regulation loss and perturbations in clock frequency and slope-compensation control.
Innovation Solution
A synchronization circuit that eliminates the PLL, using a multiplexer to select between external and internal clock signals, with a mode detection circuit, clock detection circuit, and frequency-to-current converter, along with sample-and-hold circuits to minimize perturbations and maintain stable clock and slope-compensation currents during mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Phase-Locked Loop (PLL) is used for synchronization, then the internal clock can be synchronized to an external clock, but the die area and cost increase significantly
Solution Approach 1:
The patent extracts the essential synchronization function from the complex PLL circuit and implements it using a simplified approach with a multiplexer, frequency-to-current converter, and sample-and-hold circuits. This removes unnecessary components while retaining the core synchronization capability, thereby reducing die area and cost.
Solution Approach 2:
The invention replaces the expensive and complex PLL with cheaper, simpler circuit elements such as a multiplexer and basic analog circuits. These simpler components achieve the same synchronization function with significantly reduced cost and area, even if they require different operational approaches.
2Reliability
If a PLL is used for synchronization, then clock synchronization is achieved, but stabilization time is required during mode transitions causing voltage regulation loss
Solution Approach 1:
The patent uses sample-and-hold circuits to capture and maintain the clock frequency and slope-compensation control current values before mode transitions occur. By preparing and storing these values in advance, the circuit can immediately resume stable operation after a transition without requiring stabilization time, thus preventing voltage regulation loss.
Solution Approach 2:
The frequency-to-current converter continuously monitors the external clock frequency and converts it to a control current that adjusts the internal oscillator. This feedback mechanism ensures that the internal clock remains synchronized with the external clock during mode transitions, eliminating the need for stabilization time while maintaining voltage regulation.
3Reliability
If a PLL is used for synchronization, then frequency synchronization is achieved, but frequency range is limited and die area increases
Solution Approach 1:
The patent implements a dynamic frequency-to-current converter that can adapt to a wide range of external clock frequencies. The converter dynamically adjusts the control current based on the detected frequency, allowing the internal oscillator to synchronize with external clocks across a broad frequency range without requiring multiple fixed-frequency PLL configurations, thus improving adaptability while reducing die area.
Data Source
AI summary
A synchronization circuit receives an external clock input. The circuit includes an internal oscillator; a clock detection circuit, coupled to the external clock input, for determining whether a clock signal at the external clock input is valid; circuitry for keeping the frequency of the internal oscillator constant until the clock detection circuit determines that an external clock signal is valid; and circuitry for switching the output of the synchronization circuit from the internal oscillator to the external clock input when the clock detection circuit determines than an external clock signal is valid.