PLL Frequency Access Control for Accurate Radio Modulation
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Solution Overview
Problem
In radio communication devices, frequency setting data for signal reception and transmission often collide, leading to difficulties in achieving sufficient frequency accuracy due to the use of VCXO oscillators, which are sensitive to temperature changes and aging.
Innovation Solution
A radio communication device is designed with a PLL circuit that includes a frequency divider, where a CPU and DSP control the frequency division ratio, and a PLL switch circuit manages access to prevent collisions between different data types, using a logical adder for OR operations and allowing exclusive access to the signal generator by either the CPU or DSP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If VCXO is used to modulate the reference-frequency signal for wide frequency range modulation, then modulation capability across wide frequency range is improved, but frequency accuracy deteriorates due to temperature changes and aging
Solution Approach 1:
The patent divides the modulation function into two separate paths: one using VCXO for wide frequency range modulation and another using VCO for frequency modulation. This segmentation allows each component to perform its specialized function without compromising the other, resolving the contradiction between wide frequency adaptability and frequency accuracy.
Solution Approach 2:
The patent introduces a frequency synthesis path as an intermediary mechanism that combines the outputs of VCXO and VCO through a frequency divider and phase detector. This intermediary structure allows the system to leverage the wide frequency range of VCXO while using VCO to maintain frequency accuracy through phase-locked control.
2Adaptability or versatility
If CPU and DSP both access the frequency divider to control frequency division ratio, then control flexibility is improved, but data collision occurs leading to frequency accuracy deterioration
Solution Approach 1:
The patent implements a lock signal generation mechanism that predicts when the frequency divider will be accessed and prepares the system in advance. The lock signal is generated based on the operation mode (transmission or reception) before actual access occurs, preventing data collision by ensuring only one controller (CPU or DSP) accesses the frequency divider at any given time.
Solution Approach 2:
The patent employs a feedback mechanism where the lock signal status is continuously monitored and used to control access to the frequency divider. The system feedbacks the access status to both CPU and DSP, allowing them to coordinate their operations and avoid simultaneous access that would cause data collision and frequency inaccuracies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures that frequency setting data for different purposes do not collide, resulting in improved frequency accuracy and stability, enabling effective AFC and modulation across a wide frequency range.
Implementation Method 1
a PLL (phase locked loop) circuit to implement modulation or AFC (automatic frequency control)
Implementation Method 2
a VCXO (voltage controlled crystal oscillator) as a reference-frequency signal
Implementation Method 3
The VCO serves to modulate a carrier in accordance with the modulating signal to generate a modulation-resultant signal
Data Source
AI summary
A signal generator outputs a signal whose frequency is uniquely decided by frequency data set therein. A control section can set first data in the frequency generator as frequency data. The control section can transition among an access unimplementing state, an access stand-by state, and an access implementing state. A signal processing section can set second data in the signal generator as frequency data. The signal processing section can transition between an access allowed state and an access inhibited state. The control section transfers, to the signal processing section, a signal indicative of a desire to transition to the access implementing state and a signal indicative of transition of the control section from the access implementing state. The signal processing section transfers, to the control section, a signal indicative of transition of the signal processing section between the access allowed state and the access inhibited state.